Semiconductor memory device having sense and data lines for...

Details Semiconductor memory device having sense and data lines for... Semiconductor memory device having sense and data lines for...

2000-06-21

2001-08-14

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S230060

Reexamination Certificate

active

06275407

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to improvement in read operation speed from a memory core (hereinafter called a “memory cell array”) and that in read operation margin.
A portion of conventional semiconductor memory devices incorporates a local sense amplifier provided for each column and a global sense amplifier provided for a peripheral circuit region.
FIG. 1
shows an example of a read-out circuit of a semiconductor memory device of the foregoing type.
The read-out circuit shown in
FIG. 1
incorporates a memory cell array
1
; a plurality of bit lines
2
; column select means
3
constituted by transistor switches connected to the plural bit lines
2
; local sense amplifiers
4
connected to the column select means
3
; a sense line
5
disposed along a side of the memory cell array
1
; a connecting line
6
between the sense line
5
and the peripheral circuit region; a global sense amplifier
7
formed in the peripheral circuit region; and an output circuit
8
for producing output of a read data signal.
As described later, the connecting line
6
for establishing the connection with the peripheral circuit region forms a portion of the sense line
5
. The sense line
5
and connecting line
6
form a bus line. Therefore, the sense line
5
and the connecting line
6
for establishing the connection with the peripheral circuit region are collectively called sense lines
5
and
6
.
Similarly, also data lines for transferring write data to the memory cell array
1
incorporates a first write control circuit provided in the peripheral circuit region forming the global sense amplifier
7
. Moreover, a second write control circuit is provided for each region in which the local sense amplifiers
4
is formed. Thus, write data is written on the memory cell array
1
through the first and second write control circuits and the data lines (corresponding to the sense lines
5
and
6
shown in FIG.
1
). To cause a problem experienced with the conventional technique to easily be understood, a path for transferring write data to the memory cell array
1
is omitted in FIG.
1
.
A read operation of the conventional semiconductor memory device shown in
FIG. 1
will now be described. A case will be described in which each bit line
2
is composed of a bit line pair composed of two bit lines for transferring complementary read data signals. A slight potential difference read from the memory cell appears on the bit line pair. The potential difference is amplified by the local sense amplifiers
4
connected to the bit line pair.
In
FIG. 1
, each of the column select means
3
connected to the bit lines
2
and the sense lines
5
and
6
is drawn symbolically as one line. When the complementary signals are processed, each line indicates a pair of lines.
The local sense amplifiers
4
are connected to the bit lines
2
through the column select means
3
and disposed along the side of the memory cell array
1
. The read data signal from the memory cell and amplified by the local sense amplifiers
4
is transferred to the complementary sense line
5
disposed along the side of the memory cell array
1
and the complementary connecting line
6
(hereinafter called a “sense line pair
5
and
6
) with the peripheral circuit region. Then, the read data signal is amplified by the global sense amplifier
7
disposed in the peripheral circuit region so as to be output from the output circuit
8
for the read data signal.
The signals which appear on the sense line pair
5
and
6
are distinct from the signals having a voltage amplitude in a usual complementary logic circuit. Each signal has a voltage amplitude having an intermediate voltage level as compared with the power supply voltage similarly to the read data signal from the bit line pair. The logic of the foregoing signal is determined in accordance with the positive or negative polarity of the potential difference which appears on the sense line pair
5
and
6
.
The reason why the read data signal having the intermediate voltage level which is lower than the power supply voltage is transferred, will now be described.
As described above, the sense line pair
5
is the signal line extending along the side of the memory cell array
1
. Therefore, the largest length of the sense line pair
5
is the length of one side of the memory cell array
1
.
Since a multiplicity of the local sense amplifiers
4
are connected in parallel, parasitic capacitance C which is added to the sense line pair
5
is a considerably large value. Therefore, delay time caused from R*C product which is defined by the resistance R and the parasitic capacitance C of the sense line pair
5
is a very large value as compared with that of another signal line.
When the signal lines having the considerably large R*C product are used to transfer the signals each having the voltage amplitude for the usual complementary logic circuit, power dissipation caused from charge/discharge of the parasitic capacitance is enlarged. Thus, reduction in the read operation speed caused from the R*C delay cannot be prevented.
Therefore, also the read data signals from the sense line pair
5
and
6
are the signals having the intermediate voltage level having the relatively small voltage similarly to the bit line pair. Moreover, the global sense amplifier
7
connected to the sense line pair
6
is used to convert the read data signal into the signal having the voltage amplitude for the usual complementary logic circuit. Thus, the power dissipation can be suppressed, causing the read speed to be raised.
The structure has been described in which the local sense amplifiers
4
are each connected to the respective bit lines
2
. When the number of the columns is enlarged to correspond to the trend for high capacities of the semiconductor memory devices, the local sense amplifiers
4
are each connected for several columns through a column select means
3
constituted by transistor switches.
When the number of the columns is small, a method is sometimes employed with which the local sense amplifiers
4
are not formed and the potential difference of the bit line pair read from the memory cell is directly transferred to the sense line pair
5
and
6
through the column select means
3
. In either case, the read data signal having the relatively low intermediate voltage level is transferred in the sense line pair
5
and
6
.
Referring to
FIG. 2A
, the relationship among the levels of the read data signals will now be described which is realized when three adjacent pairs A and /A, B and /B and C and /C are extracted from a plurality of the sense line pairs
5
to transfer the read data signals. As described above, the sense line pair
5
extends along the one side of the memory cell array
1
. Therefore, the parasitic capacitance of the signal line constituting the sense line pair
5
is enlarged. Also a capacitive coupling caused from an interline parasitic capacitance between adjacent signal lines is enlarged.
Therefore, the voltage level of the complementary read data signals which are transferred through the sense line
5
is changed according to the degree of the capacitive coupling between adjacent signal lines. Since each of the complementary read data signals is transferred as a relatively low intermediate voltage level, the change in the difference in the voltage level between the complementary read data signals caused from the capacitive coupling critically obstructs normal data transfer. As a matter of course, the change in the difference in the voltage level of the complementary read data signals caused from the capacitive coupling is a problem common to the sense line pair
5
and the sense line pair
6
for the connection.
Referring to
FIG. 2A
, the foregoing problem will furthermore specifically be described. An assumption is made that either of the sense line pair
5
or
6
which encounters the potential difference caused from the complementary read data signals and which has a higher voltage l

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