Semiconductor memory device having sense amplifier having improv

Details Semiconductor memory device having sense amplifier having improv Semiconductor memory device having sense amplifier having improv

1989-02-22

1990-04-10

Moffitt, James W.

Static information storage and retrieval

Addressing

Sync/clocking

365207, G11C 700

Patent

active

049166719

ABSTRACT:
A dynamic random access memory comprises memory cells (MA1-Man) and sense amplifies (SA1-SAn) in a memory array region III and memory cells (MB1-MBn) and sense amplifies (SB1-SBn) in a memory array region IV. In reading operation, first, the sense amplifiers in one region comprising a memory cell designated by an address signal are activated and then sense amplifiers in the other region are activated. As a result, since amplifying operation by the sense amplifiers is performed sequentially, a peak value of a current consumed by the amplification can be reduced.

REFERENCES:
patent: 4581720 (1986-04-01), Takemae et al.
ISSCC: "A 1Mb CMOS DRAM With Fast Page and Static Column Modes", by S. Saito et al, Session XVII, 2/15/85, pp. 252-253.
IEEE J. of Sol. St. Circuits: "A 65-ns 4-Mbit CMOS DRAM with a Twisted Driveline Sens Amplifier", by K. Kimura et al, vol. SC-22, No. 5, Oct. 1987, pp. 651-656.

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