Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-10-19
2001-12-25
Mai, Son (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S053000, C365S051000
Reexamination Certificate
active
06333868
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device, such as a dynamic random access memory and a static random access memory.
2. Description of Related Art
In a semiconductor memory device comprising a memory cell array having a number of memory cells arranged in a matrix formation, data is written in or read out of a memory cell selected through a pair of complementary bit lines extending from the memory cells in the memory cell array.
When reading data from a memory cell, data of a selected memory cell is detected by a sense amplifier, formed by a differential amplifier, through a pair of bit lines (often referred to as a bit line pair). When writing data into a memory cell, in the same way as in reading data mentioned above, data is written into a memory cell corresponding to the selected bit line pair as voltage signals applied through the sense amplifier and the bit line pair.
Because bit line pairs, each pair having mutually complementary bit lines, are arranged mutually close to each other, if data on the bit lines is interfered with the parasitic capacity between the bit lines placed close together, data reading or writing becomes unstable, which results in delay or malfunction.
To prevent the instability in data reading or writing ascribable to the parasitic capacity between bit lines, there are disclosed techniques in Japanese Patent Laid-Open Publication No. Hei 6-5081: a technique for increasing distance between bit line pairs in a memory cell array; a technique for arranging between the bit line pairs additional shielding lines different from the bit lines and not transfering data for reading/writing; and a technique for having the two component lines of a bit line pair intersect each other.
Further, Japanese Patent Laid-Open Publication No. Hei 10-69773 discloses a new idea for arranging bit line pairs in such a way that the bit line pairs, which are selected simultaneously, do not lie side by side with each other.
Further, Japanese Patent Laid-Open Publication No. 2000-82290 discloses a technique by which to arrange a shielding line between the bit lines.
These techniques can prevent the instability of data in the memory cell array.
However, these techniques are unable to stabilize data in the data bus extending externally from the memory cell array.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor memory device capable of stabilizing data in the data bus extending from the memory cell array.
According to one aspect of the present invention, there is provided a semiconductor memory device comprising a memory cell array having a plurality of memory cells on a semiconductor substrate, wherein the memory cell array includes a differential amplifier circuit serving as data input/output terminals of the memory cell array when data is written in or read from the memory cell selected; a plurality of input/output pads, provided on the semiconductor substrate, for write data to the memory cells or read data from the memory cells; and a data bus for connecting the differential amplifier and the input/output pads, wherein the data bus includes a plurality of write-only data lines dedicated to writing data to the memory cells and a plurality of read-only data lines dedicated to reading data from the memory cells, wherein the plurality of write-only data lines have mutually parallel portions and the plurality of read-only data lines have mutually parallel portions, wherein at least the parallel portions of the write-only data lines are arranged alternately with the read-only data lines in the arrangement direction of the parallel portions on the semiconductor substrate, and wherein either the write-only data lines or the read-only data lines function as shielded lines.
According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array which has a plurality of memory cells and a differential amplifier circuit, the differential amplifier circuit amplifying a data read from the memory cell and a write data to be written into the memory cell; a plurality of input/output pads which receives the write data or the read data; and a data bus, coupled between the amplifier circuit and said input/output pads, which includes a plurality of write-only data lines transferring the write data and a plurality of read-only data lines transferring the read data, wherein the write-only data lines and the read-only data lines have mutually parallel portions, wherein at least the parallel portions of said write-only data lines are arranged alternately with said read-only data lines in the arrangement direction of said parallel portions, wherein said write-only data lines are held at a predetermined potential level when said read-only data lines transfer the read data, and wherein said read-only data lines are held at a predetermined potential level when said write-only data lines transfer the write data.
REFERENCES:
patent: 5657286 (1997-08-01), Arimoto
patent: 6108264 (2000-08-01), Takahashi et al.
patent: 6212091 (2001-04-01), Kawabata et al.
Mai Son
OKI Electric Industry Co., Ltd.
Volentine & Francos, PLLC
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