Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-06-04
2002-09-17
Mai, Son (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S051000, C365S063000
Reexamination Certificate
active
06452860
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-168995, filed Jun. 6, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device having a segment type word line structure. More specifically, the invention relates to a dynamic semiconductor memory (DRAM) comprising a memory cell array that is divided into a plurality of cell array blocks. In particular, the present invention is directed to the technology for arranging wiring layers on the memory cell array.
In a conventional semiconductor memory having a multi-layered structure, multi-layered metal wiring is provided on a memory cell array. The top layer (the uppermost layer) of this metal wiring is used as data transmission lines or control signal lines (such as a column selection line). The second layer from the top is used as word lines, for example. In the case of a DRAM comprising an array of dynamic memory cells (DRAM cells) employing a stacked capacitor structure, plate electrodes of bit lines and cell capacitors are provided on the array in such a manner that the plate electrodes are located in a layer that is lower than the second metal wiring layer from the top. In a layer lower than the layer where the plate electrodes are provided, gate lines (word lines) of a DRAM cell, which are formed of polysilicon and silicide, are provided.
A segment type word line structure is known as a structure applicable to a DRAM that has a memory cell array divided into a plurality of cell array blocks. In the segment type word line structure, main word lines and sub word lines are provided at different levels. Normally, eight or four of the sub word lines are connected to one main word line.
FIG. 9
shows an example of a conventional segment type word line structure. In this example eight sub word lines are connected to one main word line, and
FIG. 9
shows part of a DRAM having this structure.
Referring to
FIG. 9
, numeral
1
denotes cell array blocks obtained by dividing a memory cell array
19
. Numeral
3
denotes a main row decoder area located at one end of the memory cell array
19
. Numeral
17
denotes a main row decoder, numeral
7
denotes a main word line driver, and numeral
2
denotes a main word line driven by the main word line driver
7
. Numeral
8
denotes a sub row decoder area, numeral
12
denotes a sub row decoder, and numeral
13
denotes a contact between one main word line
2
and the sub row decoder
12
. Numeral
14
denotes a word line drive control signal line, and numeral
15
denotes a contact between the word line drive control signal line
14
and the sub row decoder
12
. Numeral
10
denotes a sub word line driver, and numeral
11
denotes sub word lines driven by the sub word line driver
10
. Numeral
16
denotes a sense amplifier area where a bit line sense amplifier is arranged. Numeral
18
denotes a section driver, by which a cell array block selection signal for selecting the sub row decoder
12
is supplied to the word line drive control signal line
14
.
In this word line structure, it is preferable that the main word lines
2
be made of a metal wiring layer and the gate lines of the DRAM cell be used as the sub word lines
11
. In this case, the wiring pitch of the metal wiring layer used as the main word lines
2
can be determined without severe restrictions, so that an area that can be used for another purpose can be provided. In such an area, a wiring layer portion other than the main word lines
2
can be provided by utilizing the metal wiring layer described above.
FIG. 10
shows how the same metal wiring layer (one wiring layer) is used for providing main word lines
2
and other wiring lines in the DRAM structure described above. In
FIG. 10
, the same reference numbers as used in
FIG. 9
denote similar or corresponding structural components.
Referring to
FIG. 10
, the metal wiring line
9
is formed by using a metal wiring layer that is at the same level as the main word lines
2
(e.g., the second wiring layer from the top). The metal wiring line
9
is used as control signal lines other than the main word lines
2
; alternatively, it is used as power supply lines.
In this structure, the uppermost metal wiring layer (not shown) is globally arranged on the memory cell array
19
. The main word lines
2
are provided in common to the cell array blocks
1
. In other words, the main word lines
2
extend beyond the other end portion of the memory cell array
19
, i.e., beyond the end portion opposite to that where the main row decoder
17
is provided.
On the other hand, the metal wiring line
9
does not extend beyond the cell array block
1
. This means that the metal wiring line
9
does not pass across the sub row decoder
12
. The metal wiring line
9
is connected to the metal wiring
5
of another layer through a contact
6
in such a manner that the sub row decoder area
8
is connected to another sub row decoder area
8
.
Since recent DRAMs are large in capacity, the amount of charge accumulated in the entire cell capacitor is significantly large. In accordance with this, it is strictly required that the resistance components of the power supply lines be reduced with no need to increase the chip size or the number of power supply pads.
If the power supply voltage is low, the operation of the circuits is slow, accordingly. Although some of the circuits can operate at high speed by supplying a high potential to them, this entails the use of a power supply for generating the high potential, in addition to the normal power supply. Since an increase in the number of types of power supply results in a decrease in the width of each power supply line, the wiring resistance of the power supply lines is inevitably high.
To attain a high speed of data access, the circuits have to operate at high speed, and the resistance components of control signal lines (such as the drive signal line of a bit sense amplifier) must be reduced to a minimum.
When the circuits operate at high speed, the power consumption increases, resulting in noise in the circuits. To reduce this noise, the resistance components of power supply lines must be reduced.
In the DRAM of the segment type word line structure, the wiring lines other than the main word lines
2
(such as the metal wiring line
9
used as the power supply lines or control signal lines) do not extend to the outside of their cell array block
1
. Owing to this structure, it is hard to completely satisfy the requirement that the overall resistance components in signal lines and control signal lines must be reduced.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to provide a semiconductor memory device wherein the overall resistance components in power supply lines and control signal lines are reduced, thus enabling a high-speed operation.
To achieve this object, the present invention provides a semiconductor memory device which has a segment type word line structure and in which a plurality of main word lines (
2
) and a plurality of sub word lines (
11
) are arranged at different levels, the semiconductor memory device comprising: a memory cell array (
19
) divided into a plurality of cell array blocks (
1
), between which a sub row decoder area (
8
) is arranged; and a plurality of first metal wiring lines (
4
,
4
a
,
4
′) formed by use of the same wiring layer as the main word lines (
2
), passing across the sub row decoder areas (
8
) and arranged in common to the cell array blocks (
1
).
In the semiconductor memory device of the present invention, noise on the first metal wiring lines (
4
,
4
a
) used as power supply lines should preferably be bypassed to grounding lines by use of a capacitor (
31
,
41
) located at an end portion of the memory cell array (
19
).
In the semiconductor memory device of the present invention, the power supply lines and the control signal lines enable d
Ikeda Toshimi
Inaba Tsuneo
Kawabata Kuninori
Takeuchi Atsushi
Tsuchida Kenji
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Mai Son
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