Semiconductor memory device having row decoder in which...

Details Semiconductor memory device having row decoder in which... Semiconductor memory device having row decoder in which...

2007-01-02

2007-01-02

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S185170, C365S185230, C365S230060

Reexamination Certificate

active

11052792

ABSTRACT:
A semiconductor memory device includes a first, second, and third memory cell transistors in which information can be electrically rewritten, addresses of which are consecutive in a row direction. One end of a current passage in each of a first, second, and third memory cell transistors is connected to a control electrode of the first, second, and third memory cell transistors. A write voltage, a pass voltage lower than the write voltage, and a first voltage lower than the pass voltage are applied to the other ends of the first, second, and third transfer transistors. A first control section applies the first on-voltage to make the first transfer transistor conductive, to a gate of the first transfer transistor. A second control section applies a second on-voltage to make the second and third transfer transistors conductive, to gates of the second and third transfer transistors.

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patent: 2001-176284 (2001-06-01), None
patent: 2002-63795 (2002-02-01), None

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