Semiconductor memory device having redundant circuit

Details Semiconductor memory device having redundant circuit Semiconductor memory device having redundant circuit

1995-07-18

1996-10-08

Fears, Terrell W.

Static information storage and retrieval

Addressing

Plural blocks or banks

365210, 365226, G11C 1300

Patent

active

055638414

ABSTRACT:
A semiconductor memory device includes a memory cell array divided into a first memory cell array for an upper address of an input address and a second memory cell array for a lower address of the input address, a redundant cell array storing correction data, a first sense amplifier provided with respect to the first memory cell array, a first column decoder provided with respect to the first memory cell array, a second sense amplifier provided with respect to the second memory cell array, and a second column decoder provided with respect to the second memory cell array. The second sense amplifier and the second column decoder are non-selected when an access is made to the first memory cell array by the input address. The non-selected second sense amplifier and second column decoder operate as a sense amplifier and a column decoder provided with respect to the redundant cell array to thereby output the correction data from the upper address of the redundant cell array.

REFERENCES:
patent: 5245582 (1993-09-01), Kimura

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