Semiconductor memory device having redundancy circuit for...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185230, C365S189070, C365S200000

Reexamination Certificate

active

07443727

ABSTRACT:
A semiconductor memory device has: a memory cell array including a normal region and a redundancy region; a first decoder configured to decode an address signal to generate a first decode signal; a first driver configured to select a memory cell corresponding to the first decode signal in the normal region; and a second driver configured to select a memory cell in the redundancy region when a memory cell specified by the address signal is included in a replacement-target sector in the normal region. In the first driver, the first decode signal associated with the replacement-target sector is masked continuously.

REFERENCES:
patent: 5930194 (1999-07-01), Yamagata et al.
patent: 7035152 (2006-04-01), Bae et al.
patent: 7-320496 (1995-12-01), None

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