Semiconductor memory device having reduced variation of erasing

Details Semiconductor memory device having reduced variation of erasing Semiconductor memory device having reduced variation of erasing

1997-10-20

1999-08-10

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular connection

365226, G11C 1134

Patent

active

059368861

ABSTRACT:
In a semiconductor memory device comprising a plurality of memory arrays, the memory array is given a predetermined potential from a terminal via a reference line. Further, a plurality of source switches are connected to the memory arrays and the reference line. The source switches selectively transfer the predetermined potential to each of the memory arrays. In this case, each of the source switches includes a transistor having an electrical ability which is determined by a length of the reference line between each source switch and the terminal.
When the transistor is formed by a MOS transistor, the above electrical ability is specified by the ON resistance of the MOS transistor. The MOS transistors are designed so that the ON resistance becomes lower as the length of the reference line between the source switch and the terminal becomes longer. At any rate, a substantially constant voltage is supplied to each of the memory arrays irrelevant of the length of the reference line between each source switch and the terminal.

REFERENCES:
patent: 5280447 (1994-01-01), Hazen et al.
patent: 5422845 (1995-06-01), Ong
patent: 5511022 (1996-04-01), Yim et al.
patent: 5579274 (1996-11-01), Van Buskirk et al.
patent: 5719490 (1998-02-01), Germini

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