Semiconductor memory device having reduced data access time...

Details Semiconductor memory device having reduced data access time... Semiconductor memory device having reduced data access time...

1999-12-29

2001-05-01

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S185250, C365S203000

Reexamination Certificate

active

06226215

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device capable of improving row and column operations upon consecutive read operations by changing a bit line configuration and thus reducing a data access time, thereby realizing a high speed operation.
2. Discription of the Prior Art
In general, a read operation of memory device such as DRAM can be performed in accordance with the following processes.
First, a row decoding operation is carried out for selecting one of wordlines on a cell array block by supplying address signals inputted to an address buffer when an operation control signal, /RAS, is changed to an active state to the memory device and then by decoding the supplied address signals.
Next, data on the cells connected with the selected wordline are transferred to bit lines (SL, /SL) within a sense amplifier region via a bit line separating circuit. At this time, a bit line sense amplifier
5
is activated and then amplifies signals having a very small potential difference, which were loaded on the bit lines (SL, /SL) within the sense amplifier region, to a power supply voltage VCC level and a ground voltage VSS level, respectively.
Meanwhile, a pass transistor which transfers the data of the bit line, which were amplified by the bit line sense amplifier
5
, to data bus lines (DB, /DB) is switching-controlled by an output signal YI of a column decoder and thus selects one column data.
The selected column data are loaded on the data bus lines (DB, /DB) via the selectively switched pass transistor and are sensed and amplified by a data bus line sense amplifier. Then, the data bus line sense amplifier outputs the amplified data outside the device via a data output buffer and the like, thereby completing the read operation.
However, in such a conventional DRAM device which performs the read operation in accordance to the above described processes, in order that the next read operation can be formed after completing one read operation, it was possible to perform a row operation with respect to a second read command only after completing a column operation with respect to a first read command.
FIG. 1
shows a general DRAM configuration. As shown, the DRAM comprises a unit memory cell
1
consisted of a NMOS transistor NM
1
and a cell capacitor C
1
which store data thereon and which are connected between a first one side bit line BL
1
and a cell plate voltage supply terminal VCP; a first line connecting unit
2
consisted of second and third NMOS transistors (NM
2
, NM
3
) responsive to a bit line separating signal BISH for connecting or disconnecting the first bit lines (BL
1
, /BL
1
) and sense amplifier lines (SL, /SL); a second line connecting unit
3
consisted of fourth and fifth NMOS transistors (NM
4
, NM
5
) responsive to a bit line separating signal BISL for connecting or disconnecting second bit lines (BL
2
, /BL
2
) and the sense amplifier lines (SL, /SL); a precharging unit
4
for equalizing and precharging the sense amplifier lines (SL, /SL) under a control by a bit line equalizing and precharging control signal BLP; a bit line sense amplifier connected between the sense amplifier lines (SL, /SL) for performing a bit line sensing operation; and a data bus line connecting unit
6
consisted of sixth and seventh NMOS transistors responsive to a column selecting signal YI for connecting or disconnecting the sense amplifier lines (SL, /SL) and data bus lines (DB, /DB).
FIG.
2
(
a
) through
2
(
g
) show timing diagrams illustrating a bit line driving of DRAM of FIG.
1
. As shown in FIGS.
2
(
c
) and
2
(
d
) respectively, until a column operation has been completed, the bit line separating signals (BISH, BISL) and the potential of a wordline WL are still maintained at a logic high state. Therefore, both of the two signals (BISH, WL) are maintained at a switched-off state in order to perform consecutive read operations. Then, after the first bit lines (BL
1
, /BL
1
) were precharged with a predetermined potential (for example, one half of VDD potential) as shown in
2
(
e
), a /RAS signal is again applied thereto at an enable state of a logic low level as shown in FIG.
2
(
a
). At this time, when trying to read data by selecting new wordline, an interval tA between a delay time tRCD between the /RAS signal and a /CAS signal and a precharging time tRP by the /RAS signal becomes longer. As a result, there exists a problem that an access time is delayed, resulting in the limitation of a high-speed operation.
Such problem is occurred when the two bit line separating signals (BISH, BISL) are maintained at a power supply voltage VDD during precharging, and thus the bit lines (BL
1
, /BL
1
) within the memory cell region and sense amplifier lines (SL, /SL) within the sense amplifier region are activated at the same single node, as shown in FIG.
2
(
c
).
Accordingly, in the conventional DRAM configuration, since the bit lines within the memory cell region and the bit lines within the sense amplifier region are not completely separated each other, the access time is delayed and thus a high-speed operation is limited when performing consecutive read operations.
SUMMARY OF THE INVENTION
Accordingly, the present invention is made in view of the above-mentioned problem, and it is an object of the present invention to provide a high-speed operating DRAM capable of reducing a data access time by separating and individually controlling bit lines with respect to a memory cell region and a sense amplifier region and thereby carrying out row and column operations at a high speed when performing consecutive read operations.
In order to achieve the above object, in accordance to the present invention, a semiconductor memory device comprising:
a unit memory cell;
a first line connecting means responsive to a first bit line separating signal for connecting or disconnecting a first bit line within the unit memory cell and bit lines within a sense amplifier region;
a second line connecting means responsive to a second bit line separating signal for connecting or disconnecting second bit lines and bit lines within the sense amplifier region;
a first precharging means for equalizing and precharging the bit lines within the sense amplifier region under a control by a first precharging control signal;
a bit line sense amplifier connected between the bit lines within the sense amplifier region for performing a bit line sensing operation under a control by sense amplifier control signals;
a data bus line connecting means responsive to a column selecting signal for connecting or disconnecting the bit lines within the sense amplifier region and data bus lines; and
a second precharging means for equalizing and precharging the first bit lines within the unit memory cell region under a control by a second precharging control signal being characterized in that the semiconductor memory device;
wherein the first and second bit line separating signals are generated from a bit line separating signal generating means in accordance with a bank selecting signal and a sensing generating signal;
the first bit line precharging control signal is generated from a first precharging control means in accordance with the bank selecting signal and the first and second bit line separating signals; and
the second bit line precharging control signal is generated from a second precharging control means in accordance with the bank selecting signal and a /CAS signal.


REFERENCES:
patent: 5404338 (1995-04-01), Murai et al.
patent: 5636174 (1997-06-01), Rao
patent: 5790466 (2000-06-01), Hotta
patent: 5815462 (1998-09-01), Konishi et al.
patent: 5856940 (1999-01-01), Rao
patent: 5862090 (1999-01-01), Numata et al.
patent: 5901109 (1999-05-01), Miura
patent: 5909400 (1999-06-01), Bertin et al.
patent: 5914902 (1999-06-01), Lawrence et al.
patent: 6081468 (2000-06-01), Taira et al.

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