Semiconductor memory device having read/write amplifiers...

Details Semiconductor memory device having read/write amplifiers... Semiconductor memory device having read/write amplifiers...

2000-03-29

2001-06-12

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S233100

Reexamination Certificate

active

06246628

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a memory cell array divided into a plurality of segments, and having read/write amplifiers disposed for respective segments.
2. Description of the Related Art
In semiconductor memory devices, there have been demands for reduction in fabrication cost and higher speed of operation by decreasing chip area.
FIG. 5
is a schematic block diagram of a prior art synchronous DRAM.
FIG. 6
is a schematic block diagram showing a part of FIG.
5
.
In
FIG. 6
, each of local data buses LDB
1
and LDB
2
and a global data bus GDB is made up of two pairs of complementary signal lines for read and write, or one pair of complementary signal lines in common use for read and write. In a case of the two pairs, a column selection line CSL is made up of a read column selection line and a write column selection line.
For example, when contents of a memory cell
14
in a memory cell array
10
are read, a word line WL is activated to cause a very small change in a voltage of a bit line pair BL depending on the contents of the memory cell
14
, and the change is amplified by a sense amplifier
15
. Then, the column selection line (CSL) for read or write is activated to turn a column switch
11
on, and the amplified voltage of the bit line pair is transmitted through the local data bus LDB to the local data bus LDB
2
.
In a read operation, a read amplifier
21
is activated in response to activation of a read enable signal REN, the voltage of the LDB
2
is amplified by the read amplifier
21
, a resulted voltage is provided through the global data bus GDB to an I/O data buffer circuit
30
, and a data signal DATA is externally outputted from the I/O data buffer circuit
30
. In a write operation, a write amplifier
22
is activated in response to activation of a write enable signal WEN, the voltage is transmitted in a reverse direction and thereby, data is written on a memory cell
14
selected by an activated word line WL and an activated write column selection line (CSL).
The synchronous DRAM of
FIG. 5
is of a multibank architecture, and memory cell arrays of
FIG. 6
are provided to respective banks
0
to
3
. Each memory cell array is divided into segments
0
to
7
each of which has a plurality of cell columns, and read/write amplifiers
20
are disposed for respective segments.
Referring back to
FIG. 6
, one segment selection circuit
40
is selected by column address (segment address) signals CA
8
to CA
6
and their complementary signals *CA
8
to *CA
6
of the higher order 3 bits outputted from an internal column address generation circuit
51
, and the output signal REN or WEN of the segment selection circuit
40
is activated in response to activation of a read timing signal RT or a write timing signal WT from a R/W timing circuit
54
.
FIG. 7
is a logic circuit diagram of the segment selection circuit
40
.
Either signal CA
8
or *CA
8
, either signal CA
7
or *CA
7
and either signal CA
6
or *CA
6
are provided to a NAND gate
41
depending on a corresponding segment selected by the segment selection circuit
40
. For example, in a case of a segment
5
, the signals CA
8
, *CA
7
and CA
6
are provided to the NAND gate
41
. The signals RT and WT are provided to inverters
42
and
43
, respectively. The outputs of the NAND gate
41
and the inverter
42
are provided to a NOR gate
44
, and the outputs of the NAND gate
41
and the inverter
43
are provided to a NOR gate
45
. The signals REN and WEN are respectively outputted from the NOR gates
44
and
45
, respectively.
In a state where the three inputs of the NAND gate
41
are all high, its output is low, and in this state, when the read timing signal RT goes high, the output of the inverter
42
goes low, and the read enable signal REN goes high. Likewise, in a state where the three inputs of the NAND gate
41
are all high, when the write timing signal WT goes high, the write enable signal WEN goes high.
Referring back to
FIG. 6
, since not only the segment address signals CA
8
to CA
6
, but also the complementary signals thereof are provided for segment selection circuits
40
, each segment selection circuit
40
for corresponding segment has the same configuration. But, the number of the signal lines for those is large, the segment selection circuits
40
are arranged in the peripheral circuit area apart from the core circuit. Namely, the segment selection circuit
40
has 5 inputs which is larger in number than 2 outputs, the circuit
40
is arranged in the side of the segment address signals CA
8
to CA
6
and *CA
8
to *CA
6
to shorten the 5 input lines and to reduce signal line number in the core circuit.
However, since the signal lines REN and WEN are connected to each read/write amplifier
20
, in a case of
FIG. 5
for example, comparatively long interconnects amounting to 4×7×2=56 in number are laid out between the peripheral circuit and the core circuit, thus causing increase in chip area.
With such comparatively long interconnects, not only the edges of the signals REN and WEN are rounded, but also degrees of roundness of the edges are different in every chip, which reduces a timing margin of the signals. Even if buffer gates are inserted in signal lines to decrease the roundness of the edges, since signal propagation delay time of the gates is newly added, operation speed will reduce.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor memory device, having read/write amplifiers disposed for respective memory segments, whose chip are can be reduced by decreasing the number of interconnections from peripheral circuit to core circuit.
It is another object of the present invention to provide a semiconductor memory device, having read/write amplifiers disposed for respective memory segments, whose operation speed can be higher by sharpening edges of signals on lines between segment selection circuits and respective read/write amplifiers.
In the present invention, there is provided a semiconductor memory device comprising: a memory cell array, having a plurality of segments, each segment having a plurality of bit lines and a local data bus selectively coupled to one of the bit lines; a data input/output buffer circuit connected to a global data bus; read/write amplifiers, disposed for respective segments, each read/write amplifier being between the local data bus of corresponding segment and the global data bus, each read/write amplifier having a read amplifier and a write amplifier; and segment selection circuits, disposed adjacent respective read/write amplifiers, arranged in a row, each for activating corresponding read or write amplifier in response to signals on segment address lines, a read timing signal line and a write timing signal line, wherein the segment address lines, the read timing signal line and the write timing signal line are laid out along the row of the segment selection circuits.
With the present invention, since the segment selection circuits are placed adjacent to respective read/write amplifiers, and the segment address lines, the read timing signal line and the write timing signal line are placed along the row of the segment selection circuits, the number of interconnections between the peripheral circuit and the segment selection circuits in the core circuit is reduced and with this reduction, a chip area can be narrowed as compared with a prior art corresponding case.
Further, since the segment selection circuits are placed adjacent to the read/write amplifiers, the distance between both circuits is reduced as compared with a prior art case, and thereby the rounding of signal edges is reduced, achieving higher speed operation.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.


REFERENCES:
patent: 5748554 (1998-05-01), Barth et al.
patent: 5883855 (1999-03-0

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