Semiconductor memory device having pseudo row decoder

Details Semiconductor memory device having pseudo row decoder Semiconductor memory device having pseudo row decoder

1989-05-23

1990-06-05

Moffitt, James W.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, G11C 800

Patent

active

049320009

ABSTRACT:
A semiconductor memory device includes: a memory cell array including a plurality of word lines; a row pre-decoding unit responsive to a row address signal, outputting a plurality of row pre-decode signals with units of a group having signals of a number corresponding to a combination of each logic level of a predetermined plurality of bits of the row address signal; a row pre-decode wiring for transmitting the plurality of row pre-decode signals; a row main decoder responsive to one signal in each group of the plurality of row pre-decode signals, carrying out a main decoding for selecting one of the plurality of word lines; a pseudo row decoder having substantially same electrical characteristics as the row main decoder, carrying out a simulation of the main decoding in response to the plurality of row pre-decode signals output on row pre-decode wiring; and a word line driver for driving a word line selected by the row main decoder to a predetermined level. An operation of the word line driver is started in response to an activation of the pseudo row decoder, thereby excluding a possibility of an erroneous selection of a word line and preventing an unnecessary prolongation of an access time.

REFERENCES:
patent: 4399519 (1963-08-01), Masuda et al.
patent: 4731761 (1988-03-01), Kobayashi

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