Patent
1988-11-10
1990-11-13
Hille, Rolf
357 55, 357 41, H01L 2968, H01L 2906, H01L 2702
Patent
active
049705806
ABSTRACT:
A transistor (4, 5, 7, 11) is formed on a sidewall of a projection (22) which is formed on a major surface of a semiconductor substrate (1), and a capacitor (3, 5, 6) is formed on the surface of the semiconductor substrate (1) around the projection (22), to be connected to the transistor. At the forward end of the projection, an interconnection member (8) is connected to a source/drain region (11) of the transistor. Further, a transistor (4, 5, 7, 11)n is formed on an upper surface portion of a projection (22) which is formed on a major surface of a semiconductor substrate (1), and a capacitor (3, 5, 6) to be connected to the transistor is formed on a sidewall of the projection (22). An isolation oxide film (2) is formed on the major surface of the semiconductor substrate around the projection and under the capacitor. Further, a first projection (62) is formed on a major surface of a semiconductor substrate (1), and a second projection (22), which is smaller than the first projection (62), is formed on the first projection (62). A transistor (4, 5, 7, 11) is formed on a sidewall of the second projection (22) and a capacitor (3, 5, 6) is formed on a sidewall of the second projection (62) respectively, such that the transistor and the capacitor are connected with each other through an impurity layer (5) formed on an upper surface of the first projection (62).
REFERENCES:
patent: 4672410 (1987-06-01), Miura et al.
patent: 4887136 (1989-12-01), Matsuda et al.
M. Nagatomo et al., "A High Density 4M DRAM Process Using Folded Bitline Adaptive Side-Wall Isolated Capacitor (FASIC) Cell", 1986, IEDM, pp. 144-147.
Lu, "Groove-Trench MIS Capacitor", IBM Technical Disclosure Bulletin, vol. 26, No. 2, Jul. 1983, pp. 489-490.
Hille Rolf
Limanek Robert P.
Mitsubishi Denki & Kabushiki Kaisha
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