Semiconductor memory device having programmable parallel erase o

Static information storage and retrieval – Floating gate – Particular connection

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36518529, G11C 1604

Patent

active

060551844

ABSTRACT:
A flash electrically erasable and programmable read only memory (EEPROM) having a selective parallel sector erase capability (100) is disclosed. The flash EEPROM (100) includes a number of sectors (104-0 to 104-18), each of which receives an erase voltage (VCC) by way of a source switch circuit (112-0 to 112-18). The source switch circuits (112-0 to 112-18) are each enabled by logic values stored in corresponding tag registers (114-0 to 114-18). The logic values stored by the tag registers (114-0 to 114-18) can be established by the application of particular address values (A12 to A18). The logic values of the tag registers (114-0 to 114-18) can be simultaneously reset to the same value by the application of other address values (A9).

REFERENCES:
patent: 5418752 (1995-05-01), Harari et al.
patent: 5774398 (1998-06-01), Ishida
patent: 5787037 (1998-07-01), Amanai
patent: 5862079 (1999-01-01), Jinbo

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor memory device having programmable parallel erase o does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having programmable parallel erase o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having programmable parallel erase o will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-998911

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.