Semiconductor memory device having plural word lines...

Details Semiconductor memory device having plural word lines... Semiconductor memory device having plural word lines...

2008-07-23

2010-10-12

Le, Vu A (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S063000

Reexamination Certificate

active

07813179

ABSTRACT:
A semiconductor memory device includes a memory cell array which includes at least one memory unit having a preset number of memory cell transistors and a selection gate transistor on a source side, a preset number of word lines respectively connected to control gates of the preset number of memory cell transistors, and a selection gate line on a source side connected to a gate electrode of the selection gate transistor on the source side. In the semiconductor memory device, a distance C between the selection gate line at least on the source side and one of the word lines adjacent thereto is set to n*A+(n−1)B, where n is an integer greater than or equal to 2, A indicates the pitch between adjacent ones of the preset number of word lines, and B indicates the width of each of the preset number of word lines.

REFERENCES:
patent: 7244984 (2007-07-01), Kamigaichi et al.
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patent: 7687346 (2010-03-01), Yaegashi et al.
patent: 2006/0214211 (2006-09-01), Miyazaki et al.
patent: 2007/0210372 (2007-09-01), Park et al.
Jae-Duk Lee, et al., “A new Programming Disturbance Phenomenon in NAND Flash Memory by Source/Drain Hot-Electrons Generated by GIDL Current”, IEEE NCSMW 2006, pp. 31 to 33.

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