Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-06-28
2002-03-05
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S236000
Reexamination Certificate
active
06353574
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a synchronous semiconductor memory device having a pipe register, which stores and outputs data at a high speed by using a pipeline scheme.
DESCRIPTION OF THE PRIOR ARTS
In a read operation, a synchronous memory device temporarily stores data to a temporary storage unit and then outputs the data through a data output pin in synchronization with an external clock. That temporary storage unit is called a pipe register.
FIGS.
1
and
1
A-
1
D are schematic diagrams showing a synchronous memory device having a conventional pipe register.
Referring to FIGS.
1
and
1
A-
1
D the synchronous memory device includes a plurality of pipe registers, each of which is coupled to four pairs of global I/O lines and complementary global I/O lines. By combining signals of the four pairs, a common prefetch signal PFETCH[
0
:
2
] is generated. The pipe registers, coupled to eight global I/O lines and complementary global I/O lines are commonly controlled by the common prefetch signal PFETCH[
0
:
2
].
As shown in
FIG. 1A
, a prefetch signal generator
100
is coupled to four pairs of global I/O lines and complementary global I/O lines GIO<
4
>, GIOZ<
4
>, GIO<
5
>, GIOZ<
5
>, GIO<
6
>, GIOZ<
6
>, GIO<
7
>, GIOZ<
7
>.
A prefetch signal generator
110
is coupled to four pairs of global I/O lines and complementary global I/O lines GIO<
12
>, GIOZ<
12
>, GIO<
13
>, GIOZ<
13
>, GIO<
14
>, GIOZ<
14
>, GIO<
15
>, GIOZ<
15
>. Pipe registers
120
to
127
are respectively coupled to the global I/O lines and the complementary global I/O lines GIO<
0
>and GIOZ<
0
>, GIO<
1
>and GIOZ<
1
>, GIO<
2
>and GIOZ<
2
>, GIO<
3
>and GIOZ<
3
>, GIO<
4
>and GIOZ<
4
>, GIO<
5
>and GIOZ<
5
>, GIO<
6
>and GIOZ<
6
>, GIO<
7
>and GIOZ<
7
]>, and receives the common prefetch signal PFETCH[
0
:
2
] from the prefetch signal generator
100
.
Pipe registers
128
to
135
are respectively coupled to four pairs of global I/O lines and complementary global I/O lines GIO<
8
>and GIOZ<
8
>, GIO<
9
>, GIOZ<
9
>, GIO<
10
>, GIOZ<
10
>, GIO<
11
>, GIOZ<
11
>, GIO<
12
>, GIOZ<
12
>, GIO<
13
>, GIOZ<
13
>, GIO<
14
>, GIOZ<
14
>, GIO<
15
>, GIOZ<
15
>, and receives the common prefetch signal PFETCH[
0
:
2
] from the prefetch signal generator
110
.
Data output buffers
136
to
151
are coupled to output terminals of the pipe register
120
to
135
, respectively.
A pipe counter
160
generates a pipe counter signal POCNT to the pipe registers
128
to
135
. At this time, the data output is controlled by the pipe counter signal POCNT.
In such a synchronous memory device, the data on each of the global I/O lines and the complementary global I/O lines have different skews due to loads thereof. Therefore, a pulse width of the common prefetch signal PFETCH[
0
:
2
] should be widened as much as the skew between the global I/O line and the complementary global I/O line.
As a result, it is difficult for the conventional synchronous memory device to latch the data into the pipe registers in a high speed in case where the prefetch signal PFETCH[
0
:
2
] has a wide pulse width.
FIG. 2
is a circuit diagram showing a conventional pipe register. The conventional pipe register includes three storage units
200
,
210
and
220
.
As shown in
FIG. 2
, since the conventional pipe register clears data stored in storage unit
200
in response to a clear signal CL
1
, a cycle time is increased so that it is difficult to obtain a high speed of operation in the synchronous memory device.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a synchronous memory device having a pipe register, which stores and outputs data at a high speed by using a pipeline scheme.
In accordance with an aspect of the present invention, there is provided a pipe register for use in a semiconductor memory device, wherein said semiconductor memory device includes global input/output (I/O) lines, complementary global I/O lines, and pipe registers, coupled to said global I/O lines and said complementary global I/O lines, for detecting the data loaded on said global I/O lines and complementary global I/O lines to store the data, said pipe register comprising: a data detecting means, coupled to said global I/O lines and complementary global I/O lines, for detecting whether the data is loaded on said global I/O lines and complementary global I/O lines; a control signal generating means for sensing edges of the data loaded on the global I/O line and the complementary global I/O line to generate a rising edge sensing signal and a falling edge sensing signal; and a plurality of storage means for storing the data loaded on said global I/O lines and said complementary global I/O lines in response to a reset signal, the falling edge sensing signal and the rising edge sensing signal and for outputting the data in response to the pipe counter signal outputted from said pipe counting means.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:
FIGS.
1
and
1
A-
1
D are schematic diagrams illustrating a synchronous memory device having a conventional pipe register;
FIG. 2
is a circuit diagram illustrating a conventional pipe register;
FIGS.
3
and
3
A-
3
D are block diagrams illustrating a synchronous memory device having a pipe register in accordance with an embodiment of the present invention;
FIGS.
4
and
4
A-
4
D are circuit diagrams illustrating a pipe register shown in
FIG. 3
; and
FIGS. 5A and 5B
are timing charts of signals in a pipe-register shown in FIG.
4
.
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patent: 5384745 (1995-01-01), Konishi et al.
patent: 5404338 (1995-04-01), Murai et al.
patent: 5499215 (1996-03-01), Hatta
patent: 5521880 (1996-05-01), McClure
patent: 5572467 (1996-11-01), Ghassemi et al.
patent: 5594704 (1997-01-01), Konishi et al.
patent: 5657292 (1997-08-01), McClure
patent: 5895482 (1999-04-01), Toda
patent: 5946266 (1999-08-01), Iwamoto et al.
patent: 6028810 (2000-02-01), Ooishi
patent: 6105123 (2000-08-01), Raje
patent: 6160754 (2000-12-01), Suh
patent: 6-76567 (1994-03-01), None
patent: 6-203552 (1994-07-01), None
patent: 10-188553 (1998-07-01), None
patent: 11-53887 (1999-02-01), None
Hyundai Electronics Industries Co,. Ltd.
Phan Trong
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