Static information storage and retrieval – Powering – Data preservation
Patent
1997-08-01
1999-01-19
Nelms, David C.
Static information storage and retrieval
Powering
Data preservation
365226, 365227, 36518909, G11C 700
Patent
active
058620966
ABSTRACT:
A reference voltage generating circuit and a standby down-converting circuit or a tuning circuit are located in the periphery of the region where a semiconductor device is formed on a semiconductor chip, and a region including an active down-converting circuit which operates during an active cycle or a drive circuit is located adjacent to a circuit actually consuming a current. According to the semiconductor device, increase in area can be suppressed compared to the structure in which both a standby down-converting circuit or drive circuit and the tuning circuit and an active down-converting circuit are located in the vicinity of each current consuming circuit, thereby achieving efficient arrangement of the internal power supply circuitry. As a result, a semiconductor device having efficiently arranged internal power supply circuitry is provided.
REFERENCES:
patent: 5229155 (1993-07-01), Arimoto et al.
patent: 5398207 (1995-03-01), Tsuchida et al.
patent: 5426615 (1995-06-01), Tomishima et al.
patent: 5592423 (1997-01-01), Tokami
patent: 5689460 (1997-11-01), Ooishi
Ooishi Tsukasa
Setogawa Jun
Yasuda Ken'ichi
Mitsubishi Denki & Kabushiki Kaisha
Nelms David C.
Nguyen Hien
LandOfFree
Semiconductor memory device having optimally arranged internal d does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device having optimally arranged internal d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having optimally arranged internal d will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1252081