Semiconductor memory device having novel layout pattern

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257509, 257544, H01L 2976

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active

060299630

ABSTRACT:
A semiconductor memory device laid out to have a deep well of a second conductivity type formed in a semiconductor substrate of a first conductivity type, a cell array well of the first conductivity type formed on said deep well, and an isolation well of the second conductivity type formed around said cell array well to reach said deep well so as to incorporate said cell array well, thereby isolating said cell array well from said semiconductor substrate through said isolation well, wherein a circuit element for driving said cell array is formed in said isolation well.

REFERENCES:
patent: 5668755 (1997-09-01), Hidaka
S. Fujii et al., "A 45ns 16Mb DRAM with Triple-Well Structure", 1989 ISSCC Digest Technical Papers, Feb. 1989, pp. 248-249.

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