Semiconductor memory device having memory cells requiring no...

Details Semiconductor memory device having memory cells requiring no... Semiconductor memory device having memory cells requiring no...

2006-11-28

2006-11-28

Soward, Ida M. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S315000, C257S320000, C365S145000, C365S149000, C365S150000, C365S154000, C365S189090, C365S200000, C365S203000, C365S204000, C365S222000, C365S230060

Reexamination Certificate

active

07141835

ABSTRACT:
A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and second gate electrodes connected to a first (second) word line and to a second (first) node, respectively. The first (second) access transistor discharges the charges leaked from a power supply node via the first (second) p channel TFT in the OFF state in the leakage mode where the first (second) word line is inactivated and the second (first) node is at an H level.

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