Semiconductor memory device having memory cells including IG FET

Details Semiconductor memory device having memory cells including IG FET Semiconductor memory device having memory cells including IG FET

1990-09-25

1991-12-10

Hille, Rolf

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 59, 357 42, 365156, H01L 2710, H01L 2904, H01L 2702, G11C 1100

Patent

active

050722867

ABSTRACT:
A semiconductor memory device has memory cells each including first and second inverters cross-coupled to each other through first and second interconnecting conductors for forming a bistable circuit and first and second transfer gates connected between the first inverter and address signal conductors and between the second inverter and the address signal conductors, respectively. The first and second interconnecting conductors are arranged substantially point-symmetrically and have at least portions substantially parallel with each other on a surface of a substrate, and IG FETs constituting the first and second inverters have their gate electrodes arranged substantially parallel with one another and extending in a direction substantially perpendicular to the parallel portions of the first and second interconnecting conductors for the cross-coupling on the surface of the substrate.

REFERENCES:
patent: 4481524 (1984-11-01), Tsujide
patent: 4535426 (1985-08-01), Ariizumi et al.
patent: 4604639 (1986-08-01), Kinoshita
patent: 4724530 (1988-02-01), Dingwall
Okazaki et al., "A 30 ns 256 K Full CMOS SRAM", 1986, IEEE Int. Solid State Circuits Conference, pp. 204-205, 349.

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