Semiconductor memory device having memory cells formed of one tr

Details Semiconductor memory device having memory cells formed of one tr Semiconductor memory device having memory cells formed of one tr

1993-04-21

1994-08-02

Fears, Terrell W.

Electricity: electrical systems and devices

Control circuits for electromagnetic devices

Systems for magnetizing, demagnetizing, or controlling the...

36518901, G11C 1124

Patent

active

053351967

ABSTRACT:
A semiconductor memory device having transistors and capacitors on a semiconductor substrate with the lower electrodes and the contact holes for connection with the sources of the transistors formed on a self-alignment basis and a method of producing the same are disclosed. The transistor of the semiconductor memory device formed on the semiconductor substrate has a first insulating layer, a gate electrode, a source portion and a drain portion. The source and drain portions dispose in the vicinity of the gate electrode, on opposite sides of each other relative to the gate electrode, under the first insulating layer and in the semiconductor substrate. The capacitor of the semiconductor memory device has a lower electrode connecting with the source portion, a second insulating layer between the lower electrode and the upper surface of the gate electrode, a third insulating layer covering the source-side sidewall of the second insulating layer and that of the gate electrode, and a fourth insulating layer covering the drain-side of the upper surface and the source-side sidewall of the second insulating layer and that of the gate electrode. Displacement from the upper surface of the insulator on the gate electrode to the source portion is large and the slope is long enough so that the lower electrode of the capacitors formed on the slope may have a relatively large surface and the clearance between the gate electrode and the contact hole for connection with the lower electrode may be significantly reduced.

REFERENCES:
patent: 4801989 (1989-01-01), Taguchi

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