Excavating
Patent
1990-01-31
1992-08-18
Smith, Jerry
Excavating
371 48, 371 491, 371 402, 365200, G06F 1110
Patent
active
051405970
ABSTRACT:
A semiconductor memory device is provided with a memory cell array having a plurality of memory cells formed by a mask ROM. The memory cell array has a data area in which stored data of n bits is stored and a parity area in which a one-bit parity code corresponding to the stored data is stored. A control circuit supplies the memory cell array with an address and reads out the stored data and the one-bit parity code designated by the address. A parity check circuit determines whether the data read out from the memory cell array has a bit error and generates a correction bit responsive thereto. A memory stores predetermined indicating data indicating which of the n bits of the stored data is defective. A data correction circuit then corrects one of the n bits of the data indicated by the predetermined indicating data in response to the correction bit generated by the parity check circuit.
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Fujitsu Limited
Hua Ly V.
Smith Jerry
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