Semiconductor memory device having improved wiring architecture

Details Semiconductor memory device having improved wiring architecture Semiconductor memory device having improved wiring architecture

1996-07-08

1998-09-15

Nelms, David C.

Static information storage and retrieval

Interconnection arrangements

365 51, G11C 506

Patent

active

058089306

ABSTRACT:
In a line configuration of each memory cell array employed in a semiconductor memory device, a pair of bit line signal input/output lines or a pair of input/output data lines for transmitting complementary signals are disposed on both sides of and adjacent the global word line so as to cancel the influence of the global word line. By these configurations, the number of shielded lines may be reduced and the width of each line and the interval between the lines are arrayed for preventing the respective lines from breaking or being short-circuited.

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patent: 5379248 (1995-01-01), Wade et al.
patent: 5563820 (1996-10-01), Wade et al.
Shiomi et al., "New Bit Line Arthitecture for Ultra High Speed SRAMs," IEEE 1991 Custom Integrated Circuits Conference, May 12, 1991, pp. 10.4.1-10.4.4.
Shiomi et al., "A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped Bit Line Architecture", IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993, pp. 1362-1369.
Takahashi et al., "New Bit Line Architecture for Ultra High Speed SRAMs--T-Shaped Bit Line and its real application to 256 K BiCOMS TTL SRAMs", Institute of Electronics, Information and Communication Engineers, Jun. 21, 1991, pp. 117-123.

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