Semiconductor memory device having improved interconnection stru

Details Semiconductor memory device having improved interconnection stru Semiconductor memory device having improved interconnection stru

1987-09-09

1989-05-23

James, Andrew J.

357 41, 357 236, 357 59, H01L 2710, H01L 2702, H01L 2978, H01L 2904

Patent

active

048335185

ABSTRACT:
A memory cell array is divided into two groups, one bit line of a pair of bit lines is connected to corresponding memory cells in the first group of the memory cell array, and the other bit line thereof is connected to corresponding memory cells in the second group of the memory cell array.

REFERENCES:
patent: 4412237 (1983-10-01), Matsumura et al.

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