Semiconductor memory device having high speed data read...

Details Semiconductor memory device having high speed data read... Semiconductor memory device having high speed data read...

2000-12-19

2003-03-11

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189110, C365S189070

Reexamination Certificate

active

06532174

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and, more particularly, to a semiconductor memory device that can perform a highly reliable data read operation at a high speed.
2. Description of the Related Art
As a semiconductor memory device that reads data by comparing a memory cell with a read reference cell, there is a nonvolatile semiconductor memory device that stores data utilizing differences in threshold voltage.
In a stacked-gate nonvolatile semiconductor memory device such as a flash memory, for instance, data is stored utilizing variations in threshold voltage depending on the number of electrons in a floating gate. In such a case, the threshold voltage is set as follows.
In a case of memory cells that store digital data, the threshold voltage of the memory cells that constitute a memory cell array is set within one of two threshold voltage ranges. The threshold voltage of a memory cell that stores “1” is lower than a first threshold voltage. The threshold voltage of a memory cell that stores “0” is higher than a second threshold voltage. Here, the first threshold voltage is lower than the second threshold voltage. Meanwhile, the threshold voltage of a read reference cell is set between the first and second threshold voltages in advance.
The difference between the threshold voltage of the reference cell and the threshold voltage of a memory cell that stores “1” or “0” serves as a threshold voltage margin (hereinafter referred to as “read margin”) for reading the data “1” or “0”. The above relationship between threshold voltages also holds in a semiconductor memory device that stores multilevel data in memory cells.
Next, a data reading method in which data is read in accordance with the difference between the threshold voltages of the reference cell and a memory cell will be described. Cell currents flowing through the memory cell and the reference cell are converted into voltages, and a comparator circuit
11
then compares the voltages. As shown in
FIG. 1
, a comparison result signal RS depending on the relationship between the threshold voltages of the reference cell and the memory cell is obtained. In accordance with the comparison result signal RS, it is determined whether the read data is “1” or “0”. In this method, it is essential to make the comparison with the conditions of the gates, the drains, the sources, and the back biases being all equalized between the reference cell and the memory cell to be read.
Meanwhile, as portable information devices have become widely spread in recent years, there has been an increasing demand for nonvolatile semiconductor memory devices that performs at lower voltages. To achieve a low voltage operation, the word line is boosted so as to increase the cell current difference between the reference cell and a memory cell from which data is read out. The boosting is performed at the start of a read operation so as to reduce the standby current of the nonvolatile semiconductor memory device. Likewise, the biasing of the bit line is performed only during a data read operation, and no biasing is performed while standing by.
The timings of boosting the word line and biasing the bit line are controlled by a timing circuit.
However, since the distance between a memory cell and a word line driver or a bit line bias circuit varies depending on the location of the memory cell, there is a difference in signal transmission time among memory cells. As a result, at the early stage of a data read operation, differences are also caused to the bias conditions of the gates and drains. To solve this problem, a sufficient time is maintained so as to make uniform the bias conditions between the gate and drain of a memory cell prior to the cell current comparison between the reference cell and the memory cell. However, this is a hindrance to a high-speed read operation.
In a case where no extra time is ensured before the cell current comparison so as to perform a high-speed read operation, on the other hand, there is a problem that the read margin is reduced. Since the read margin depends on the location of each memory cell, problems (described later) might arise.
FIG. 1
shows the structure of a conventional nonvolatile semiconductor memory device. This nonvolatile semiconductor memory device comprises a timing circuit
1
, a word line driver
3
, a bit line decoder
5
, a reference word line driver
7
, cascode-type sense circuits
9
and
10
, the comparator circuit
11
, dummy cells
12
, memory cells MC
0
to MCn, a reference cell RC, a word line WL, a reference word line RWL, bit lines BL
0
to BLn, and a reference bit line RBL.
The word line driver
3
and the reference word line driver
7
are connected to the timing circuit
1
, and drive the word line WL and the reference word line RWL, respectively. A booster power voltage VPP is supplied to the word line driver
3
and the reference word line driver
7
. An activation signal AS for activating each driver is supplied from the timing circuit
1
. The word line driver
3
selects the word line WL for activation, in accordance with a select signal SS.
The gate of each of the memory cells MC
0
to MCn is connected to the word line WL, while the source is grounded. The bit lines BL
0
to BLn are selectively activated by the bit line decoder
5
, in accordance with column address signals CA
0
and CA
1
and their inversion signals CA
0
B and CA
1
B. The bit line decoder
5
will be described later in greater detail.
Like the memory cells MC
0
to MCn, the gate of the reference cell RC is connected to the reference word line RWL, while the source is grounded. The drain of the reference cell RC is connected to the reference bit line RBL. The dummy cells
12
as the equivalents of the memory cells MC
0
to MC(n−1) are also connected to the reference word line RWL.
The cascode sense circuit
9
is connected to the bit line decoder
5
, and the cascode sense circuit
10
is connected to the reference bit line RBL. The cascode sense circuits
9
and
10
will be described later in greater detail. The comparator circuit
11
is connected to the cascode sense circuits
9
and
10
.
FIG. 2
is a circuit diagram showing the structure of the bit line decoder
5
. In this example shown in
FIG. 2
, four memory cells MC
0
to MC
3
are connected to the word line WL. As shown in
FIG. 2
, n-channel MOS transistors NT
7
and NT
8
are connected in series to the bit line BL
0
. The column address signal CA
0
B is supplied to the gate of the n-channel MOS transistor NT
7
, while the column address signal CA
1
B is supplied to the gate of the n-channel MOS transistor NT
8
.
In parallel with the n-channel MOS transistor NT
7
, an n-channel MOS transistor NT
9
is connected to the bit line BL
1
, and the column address signal CA
0
is supplied to the gate of the n-channel MOS transistor NT
9
.
Likewise, n-channel MOS transistors NT
10
and NT
11
are connected in series to the bit line BL
2
. The column address signal CA
0
B is supplied to the gate of the n-channel MOS transistor NT
10
, while the column address signal CA
1
is supplied to the gate of the n-channel MOS transistor NT
11
. In parallel with the n-channel MOS transistor NT
10
, an n-channel MOS transistor NT
12
is connected to the bit line BL
3
, and the column address signal CA
0
is supplied to the gate of the n-channel MOS transistor NT
12
.
The bit line decoder
5
having the above structure operates in the following manner. When high-level column address signals CA
0
B and CA
1
B are supplied to the bit line decoder
5
, the bit line BL
0
is activated, and data DATAB is read out from the memory cell MC
0
.
When high-level column address signals CA
0
and CA
1
B are supplied to the bit line decoder
5
, the bit line BL
1
is activated, and the data DATAB is read out from the memory cell MC
1
. When high-level column address signals CA
0
B and CA
1
are supplied to the bit line decoder
5
, the bit line BL
2
is activated, and the data DATAB is read out from

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