Semiconductor memory device having hierarchical word line...

Details Semiconductor memory device having hierarchical word line... Semiconductor memory device having hierarchical word line...

2002-05-07

2003-07-22

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189110, C365S189090

Reexamination Certificate

active

06597624

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a semiconductor memory device having a divided word line structure (hierarchical word line structure) that a word line is divided into a main word line and a sub word line. More particularly, the present invention relates to a configuration for driving a sub word line to a selected state.
2. Description of the Background Art
FIG. 10
is a diagram schematically showing the configuration of an array portion of a conventional semiconductor memory device. In
FIG. 10
, in the memory cell array portion, memory cells MC are arranged in a matrix of rows and columns. Sub word lines SWL are arranged in correspondence to rows of memory cells MC. In
FIG. 10
, sub word lines SWL
00
, SWL
01
, SWL
10
, and SWL
11
are representatively shown. Although not clearly shown, memory cells MC are divided into a plurality of memory blocks along the row direction (direction in which the sub word line extends). In each memory block, sub word line SWL is arranged in correspondence to a memory cell row, and memory cells MC in the corresponding row are connected to sub word line SWL.
In each memory block, a main word line ZMWL is arranged in correspondence to a predetermined number of sub word lines. Main word line ZMWL is arranged commonly to memory blocks aligned in the row direction.
In correspondence to sub word line SWL, a sub word driver SWD is arranged. In
FIG. 10
, sub word drivers SWD
00
, SWD
01
, SWD
10
, and SWD
11
arranged in correspondence to sub word lines SWL
00
, SWL
01
, SWL
10
, and SWL
11
, respectively, are shown representatively.
Each of sub word drivers SWD
00
, SWD
01
, SWD
10
, and SWD
11
drives a corresponding sub word line to a selected state in accordance with a signal potential on main word line ZMWL and a row selection signal RSL (sub decode signals SD and ZSD). Row selection signal RSL includes complementary sub decode signals SD and ZSD and designates one sub word line in a set of sub word lines arranged, in the column direction, in correspondence to one main word line. Specifically, in the layout shown in
FIG. 10
, according to sub decode signals SD and ZSD, one of sub word lines SWL
00
and SWL
10
is designated and one of sub word lines SWL
01
and SWL
11
is selected.
By disposing one main word line ZMWL in correspondence to a plurality of rows of memory cells MC, pitch condition on main word lines ZMWL is relaxed. To main word line ZMWL, only sub word drivers are connected, but memory cells MC are not connected. Therefore, the load on main word line ZMWL can be reduced, and a word line can be driven to the selected state at high speed. The configuration that the word line is divided into main word line ZMWL and sub word lines SWL (generically indicating sub word lines SWL
00
, . . . , and SWL
11
) is called a divided word line structure or hierarchical word line structure.
In
FIG. 10
, a bit line pair BLP arranged in correspondence to a column of memory cells is shown. Bit line pair BLP includes complementary bit lines BL and /BL, and a memory cell MC is connected to one of bit lines BL and /BL.
FIG. 11
is a diagram showing the configuration of sub word driver SWD illustrated in FIG.
10
. In
FIG. 11
, sub word driver SWD includes: a P-channel MOS transistor (insulated gate field effect transistor) Q
1
which is made conductive, when the signal potential on main word line ZMWL is at the L level (ground voltage Vss level), to transmit sub decode signal SD onto sub word line SWL; an N-channel MOS transistor Q
2
which is made conductive, when the signal potential on main word line ZMWL is at the H level (high voltage Vpp level), to drive sub word line SWL to a non-selected state (ground voltage Vss level); and an N-channel MOS transistor Q
3
which is made conductive, when complementary sub decode signal ZSD is at the H level (array power supply voltage Vdda level), to drive sub word line SWL to a non-selected state (ground voltage Vss level).
Sub decode signal SD changes between a high voltage Vpp and a ground voltage Vss, and complementary sub decode signal ZSD changes between an array power supply voltage Vdda and ground voltage Vss. High voltage Vpp is higher than array power supply voltage Vdda. High voltage Vpp is supplied to a selected sub word line SWL by sub decode signal SD for the following reason.
As shown in
FIG. 11
, each memory cell MC includes a memory capacitor MQ for storing information and an access transistor MT which is made conductive, in response to the signal potential on sub word line SWL, to connect memory capacitor MQ to a corresponding bit line BL (or /BL). Access transistor MT is formed of an N-channel MOS transistor. The voltage level of H-level data transmitted to bit lines BL and /BL is the array power supply voltage Vdda level. In the case of writing H-level data to memory capacitor MQ, it is therefore necessary to prevent that the voltage level of the H-level data in memory capacitor MQ drops due to a threshold voltage loss in access transistor MT for the following reasons:
(i) At the time of reading memory cell data, a sufficiently large voltage change has to be brought about on a corresponding bit line.
(ii) A voltage applied to the main electrode (cell plate electrode) of a memory capacitor is usually an intermediate voltage between the array power supply voltage and the ground voltage, and a precharge voltage on a bit line is similarly at the intermediate voltage level. Consequently, by equaling a bit line voltage change when H-level data is read on a corresponding bit line with that when L-level data is read, a sense margin of a not-shown sense amplifier is increased.
(iii) A sufficient amount of charges is accumulated in memory capacitor MQ, to prevent the stored information from being lost due to a leak current or the like. A sense amplifier is arranged in correspondence to each bit line pair and activated to amplify the difference between voltages of bit lines in a corresponding pair.
In order to prevent the threshold voltage loss in voltage level of the H-level data, high voltage Vpp higher than array power supply voltage Vdda is supplied onto a selected sub word line SWL. Main word line ZMWL is set to the high voltage Vpp level in a non-selected state for the reason that even if sub decode signal SD at the high voltage Vpp level is applied, in sub word driver SWD, P-channel MOS transistor Q
1
is set in the off state with reliability to hold the corresponding sub word line SWL in the non-selected state.
In the configuration of sub word driver SWD shown in
FIG. 11
, when main word line ZMWL is at the high voltage Vpp level, MOS transistor Q
1
is in the off state and MOS transistor Q
2
is in the on state. In this state, since MOS transistor Q
1
is in the off state and MOS transistor Q
2
is in the on state, irrespective of the logic level of each of sub decode signals SD and ZSD, sub word line SWL is driven to the ground voltage Vss level. Therefore, when main word line ZMWL is at the high voltage Vpp level in the non-selected state, corresponding sub word line SWL is held at the ground voltage Vss level or the non-selected state.
On the other hand, when main word line ZMWL is driven to the selected state at the ground voltage Vss level, MOS transistor Q
1
is turned on or off, and MOS transistor Q
2
is turned off. When sub decode signal SD is at the high voltage Vpp level, MOS transistor Q
1
is turned on and sub decode signal SD at the high voltage Vpp level is transmitted to sub word line SWL.
On the other hand, when sub decode signal SD is in the non-selected state at the ground voltage Vss level, the gate and source of MOS transistor Q
1
become at the same voltage level and MOS transistor Q
1
is turned off. In this state, both MOS transistors Q
1
and Q
2
are in the off state. Sub decode signal ZSD is at the array power supply voltage Vdda level at this time, and MOS transistor Q
3
is turned on to drive not-selected sub word line SWL to the ground voltage Vss level. Th

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