Semiconductor memory device having hierarchical row selecting li

Details Semiconductor memory device having hierarchical row selecting li Semiconductor memory device having hierarchical row selecting li

1989-08-29

1990-12-11

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, G11C 800, G11C 11407, G11C 11408

Patent

active

049775383

ABSTRACT:
A memory cell array of this semiconductor memory device is divided into a plurality of large memory cell groups, and each of the large memory cell groups is further divided into a plurality of small memory cell groups. A plurality of main row-selecting lines, a plurality of sub row-selecting lines and a plurality of word lines are provided in the memory cell array, each of the large memory cell groups and each of the small memory cell groups, respectively. Main global decoders select one of the main row-selecting lines in response to an internal address signal. Sub global decoders select a sub row-selecting line associated with the selected main row-selecting line in the large memory cell group selected by a large memory cell group selecting signal. Local decoders select a word line associated with the selected sub row-selecting line in the small memory cell group selected by a small memory cell group selecting signal.

REFERENCES:
patent: 4542486 (1985-09-01), Anami et al.
patent: 4807191 (1989-02-01), Flannagan
patent: 4875190 (1989-10-01), Sakano
List et al, "A 25ns Full-CMOS 1Mb SRAM", 1988 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (1988) pp. 178-179 and 358.
Sasaki et al., "A 15ns 1Mb CMOS SRAM", 1988 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (1988), pp. 174-175 and 355.
Wada et al, "A 14ns 1Mb CMOS SRAM with Variable Bit-Organization", 1988 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (1988), pp. 252-253 and 393.
Hung Chang Lin et al, "An Optimized Output Stage for MOS Integrated Circuits", IEEE International Solid State Circuits Conf., Digest of Technical Papers (1975), pp. 106-109, 185-186.

Affiliated with

Also associated with

Rating

Semiconductor memory device having hierarchical row selecting li does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having hierarchical row selecting li, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having hierarchical row selecting li will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-393741