Semiconductor memory device having hierarchical bit line structu

Details Semiconductor memory device having hierarchical bit line structu Semiconductor memory device having hierarchical bit line structu

1997-07-14

1998-09-29

Hoang, Huan

Static information storage and retrieval

Interconnection arrangements

365 72, 365 51, 365149, G11C 506

Patent

active

058154280

ABSTRACT:
A semiconductor memory device includes a semiconductor substrate, a plurality of sub bit line pairs formed on the semiconductor substrate, a main bit line pair formed at a layer above the plurality of sub bit line pairs, a plurality of selecting transistors, a plurality of word lines located to cross the sub bit line pairs, and a plurality of memory cells. Each selecting transistor is provided corresponding to one sub bit line and has one source/drain region connected to a corresponding sub bit line. At a layer above the other source/drain region of the selecting transistor, an intermediate layer is formed in the same layer as that of a storage node of memory cell. The intermediate layer is connected to the other source/drain region of the selecting transistor through a contact hole formed beneath it. The intermediate layer is further connected to the main bit line through another contact hole formed on the intermediate layer.

REFERENCES:
patent: 5495440 (1996-02-01), Asakura
"Nand-Structured Cell Technologies for 256 Mb Drams", Yamada et al., Technical Report of IEICE SDM94-18, ICD94-29 (1994-05) pp, 13-18.
"Nand-Structured Cell Technologies for Low Cost 256 Mb Drams", Hamamoto et al., IEDM 93, 1993 pp. 643-646.

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