Semiconductor memory device having folded bit line array and an

Details Semiconductor memory device having folded bit line array and an Semiconductor memory device having folded bit line array and an

1996-03-13

1998-06-02

Nelms, David C.

Static information storage and retrieval

Interconnection arrangements

365 51, 365149, 36518907, 36518908, G11C 506

Patent

active

057611092

ABSTRACT:
A dynamic semiconductor memory device according to the present invention comprises at least first and second memory cell arrays having a plurality of memory cells selectively arranged at respective intersections of a plurality of word lines and a plurality of bit lines, a first sense amplifier section connected at an end of the first cell array to a plurality of bit line pairs formed by part of the plurality of bit lines of the first cell array, the plurality of bit line pairs having a folded bit line configuration, a second sense amplifier section connected to sets of bit line pairs, each formed by one of the remaining bit lines of the first cell array and one of part of the plurality of bit lines of the second cell array, the plurality of bit line pairs having an open bit line configuration, and a correction circuit for correcting the level of ease for reading data "0" and that of reading data "1".

REFERENCES:
patent: 4656613 (1987-04-01), Norwood et al.
patent: 5339273 (1994-08-01), Taguchi
patent: 5550769 (1996-08-01), Hidaka et al.
patent: 5555519 (1996-09-01), Takashima et al.
patent: 5602772 (1997-02-01), Nakano et al.
patent: 5625234 (1997-04-01), Suzuki et al.
IEICE Transaction on Electronics, vol. E77-C, No. 5, pp. 869-872, May 1, 1994, D. Takashima, et al., "Open/Folded Bit-Line Arrangement For Ultra-High Density Dram's".

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