Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-04-03
2007-04-03
Kim, Hong (Department: 2185)
Static information storage and retrieval
Addressing
Sync/clocking
C365S193000, C710S071000, C713S400000, C711S105000, C711S167000
Reexamination Certificate
active
10273512
ABSTRACT:
A semiconductor memory system, a memory control circuit and a semiconductor memory device are disclosed. The system includes a memory control circuit for generating a data strobe signal and a data load signal in synchronization with each other. The memory circuit, which can be an SDRAM memory circuit, receives the data strobe signal and the data load signal and writes data in response to the two synchronous signals. Because the signal are synchronous, parameters introduced by timing variations caused by different signal domains are eliminated. As a result, high-frequency operation of the system is greatly improved.
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Jang Seong-Jin
Kwak Jin-Seok
Kim Hong
Mills & Onello LLP
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