Semiconductor memory device having error detection/correction fu

Details Semiconductor memory device having error detection/correction fu Semiconductor memory device having error detection/correction fu

1985-12-03

1987-11-10

Smith, Jerry

Excavating

371 51, G06F 1110

Patent

active

047062495

ABSTRACT:
In the semiconductor memory device of the invention, a normal voltage detecting circuit and a high voltage detecting circuit are connected to a terminal for the purpose of receiving a write enable signal. When a signal of normal level is supplied to the terminal, the circuit controls data read or write with respect to a memory cell array in accordance with the level of the write enable signal. An error correction code circuit is rendered operative, and a soft error generated in data read from the memory cell array is corrected. When a high voltage is applied to the terminal, the circuit sets the memory device in the read mode. The circuit detects application of the high voltage to the terminal and supplies a predetermined signal to an ECC control circuit. In response to the signal, the ECC control circuit stops the operation of the ECC circuit. Data without any correction of soft errors is output from the memory device, and testing of hard errors is simplified.

REFERENCES:
patent: 3836957 (1974-09-01), Duke
patent: 4058851 (1977-11-01), Scheuneman
patent: 4296494 (1981-10-01), Ishikawa
patent: 4336611 (1982-06-01), Bernhardt
patent: 4412314 (1983-10-01), Proebsting
patent: 4461003 (1984-07-01), Tamaki
patent: 4493081 (1985-01-01), Schmidt
Osman, "Error-Correction Technique for Random-Access Memories," IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982.

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