Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2007-10-02
2007-10-02
Elms, Richard T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S210130, C365S189080
Reexamination Certificate
active
10930767
ABSTRACT:
A semiconductor device includes a memory cell array and first and second replica bit lines. A plurality of memory cells are arranged in an array form on the memory cell array. The first replica bit line is configured by wirings having the same wiring width and wiring intervals as bit lines configuring the memory cell array and is operated to generate a read timing signal. The second replica bit line is configured by wirings having the same wiring width and wiring intervals as the bit lines configuring the memory cell array and is operated to generate a write timing signal.
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U.S. Appl. No. 11/434,064, filed May 16, 2006, Hirabayashi.
Elms Richard T.
Kabushiki Kaisha Toshiba
Nguyen Dang
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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