Semiconductor memory device having dummy bit and word lines

Details Semiconductor memory device having dummy bit and word lines Semiconductor memory device having dummy bit and word lines

1999-04-09

2000-10-03

Nelms, David

Static information storage and retrieval

Interconnection arrangements

36518909, 365200, 365149, 257296, G11C 506

Patent

active

06128209&

ABSTRACT:
A semiconductor memory device includes a semiconductor substrate having a memory cell array area, a peripheral circuit area surrounding the memory cell array area, and a boundary area located between the memory cell array area. The peripheral circuit area, the memory cell array area, and the boundary area are located on a principle surface of the semiconductor substrate. The device also includes word lines which extend parallel to each other in a first direction, a dummy word line which extends in the first direction, and an insulation layer covering over the word lines and the dummy word line. The device further includes bit lines and a dummy bit line respectively formed over the insulation layer and extending parallel to each other in a second direction substantially perpendicular to the first direction. Memory cells are located in the memory cell array area at intersections of the word lines and the bit lines, each of which includes a capacitor and a switching transistor. The dummy word line and the dummy bit line receive a same potential.

REFERENCES:
patent: 5281555 (1994-01-01), Cho
patent: 5361234 (1994-11-01), Iwase
patent: 5867434 (1999-02-01), Oh et al.
patent: 5945702 (1999-08-01), Nakanishi
patent: 5982695 (1999-11-01), Mukai

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