Semiconductor memory device having dual word line structure

Details Semiconductor memory device having dual word line structure Semiconductor memory device having dual word line structure

1993-10-06

1995-05-16

Popek, Joseph A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 36518908, G11C 1712

Patent

active

054167485

ABSTRACT:
A dynamic random access memory device of a dual word line structure is disclosed, which comprises a plurality of memory array blocks, each of the memory array blocks including at least one main-word line, a plurality of sub-word lines, a plurality of sub-word drivers having an input node connected to the main-word line, an output node connected to an associated one of the sub-word lines and a power node, each of the sub-word drivers responding to an active level of the main-word line to drive the associated sub-word line with a power voltage supplied to the power node, and a decoding unit for, when activated, supplying the power voltage to the power nodes of the sub-word line drivers, and the decoding unit of one of the memory array blocks being activated in response to address information.

REFERENCES:
patent: 4935898 (1990-06-01), Miyaoka et al.
patent: 5140550 (1992-08-01), Miyaoka et al.
patent: 5274597 (1993-12-01), Ohbayashi et al.
K. Noda et al., "A Boosted Dual Word-line Decoding Scheme for 256Mb DRAMSs", 1992 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 112-113.

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