Semiconductor memory device having dual word line configuration

Details Semiconductor memory device having dual word line configuration Semiconductor memory device having dual word line configuration

1995-09-29

1997-01-21

Zarabian, Amir

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365149, 365200, 3652257, G11C 800

Patent

active

055965423

ABSTRACT:
In a semiconductor memory device including: a plurality of sub word lines, a plurality of sub word decoders each connected to one of the sub word lines, a plurality of pairs of main word lines each pair connected to a number of the sub word decoders, and a plurality of main word decoders each connected to one of the pairs of main word lines, each of the main word decoders sets voltages at a respective pair of the pairs of main word lines different from each other in a selection mode and sets the voltages at a respective pair of the pairs of main word lines the same as each other in a non-selection mode.

REFERENCES:
patent: 5467316 (1995-11-01), Kim et al.
Tadahiko Sugibayashi et al., "A 30ns 256Mb DRAM with Multi-Divided Array Structure", Digest of IEEE International Solid-State Circuits Conference, pp. 50-51, 1993/session 3.

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