Semiconductor memory device having dual mode operation

Static information storage and retrieval – Addressing – Plural blocks or banks

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Details

36518901, 36523006, 3652385, G11C 700, G11C 800

Patent

active

054973520

ABSTRACT:
An improvement of a semiconductor memory device capable of designating a block write mode in which writing is effected simultaneously to a plurality of memory cells unitized by predetermined numbers and connected respectively to a plurality of column lines. Data lines correspond to a predetermined number of memory cells. The data lines and the column lines are selectively connected to each other by switches. During a block write mode, a predetermined number of column lines are simultaneously connected to the data lines corresponding thereto. During the other mode, a control unit controls the switches to connect some of the predetermined number of column liens to the data lines corresponding thereto. During the mode other than the block write mode, only a part of the predetermined number column lines are connected to the data lines, thereby reducing electric power consumption.

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