Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1989-06-15
1991-01-01
Clawson, Jr., Joseph E.
Static information storage and retrieval
Addressing
Plural blocks or banks
36523004, 36523006, 365185, G11C 802
Patent
active
049823728
ABSTRACT:
A memory array is divided into first and second memory array blocks. Two word line and/or bit line selection decoders are provided on each memory array block. One of two word line and/or bit line selection decoders is provided between two memory array blocks and the other is provided on the opposite side of the one word line selection decoder about the memory array block. A plurality of word lines in the memory array blocks are alternately connected to the one word line selection decoder and the other word line selection decoder.
REFERENCES:
patent: 4613958 (1986-09-01), Culican et al.
patent: 4783764 (1988-11-01), Tsuchiya et al.
patent: 4818900 (1989-04-01), Klass et al.
patent: 4875196 (1989-10-01), Spaderna et al.
Clawson Jr. Joseph E.
Mitsubishi Denki & Kabushiki Kaisha
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