Semiconductor memory device having divided word line structure

Details Semiconductor memory device having divided word line structure Semiconductor memory device having divided word line structure

2002-08-07

2004-03-30

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S154000, C365S042000

Reexamination Certificate

active

06714478

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a local decoder in a semiconductor memory device having a divided word line structure, which is used in a Static Random Access Memory (SRAM) and the like.
In a semiconductor memory device such as an SRAM and a Dynamic Random Access Memory (DRAM) having a large-scale memory array, a so-called “divided word line structure” is known that is directed to suppress delay in signal propagation on a word line and to reduce the circuit scale of a decode circuit effecting word line selection. An example of the divided word line structure is disclosed in Japanese Patent Laying-Open No. 59-72695 (hereinafter also referred to as “Conventional Example 1”).
FIGS. 5 and 6
are the first and second conceptual diagrams each illustrating a divided word line structure shown in Conventional Example 1.
A semiconductor memory device shown in
FIG. 5
includes a memory array divided into four memory blocks
5
a
to
5
d
, a global decoder
10
, and local decoder zones
20
a
to
20
d
provided in correspondence to memory blocks
5
a
to
5
d
, respectively. Memory cells MC are arranged in a matrix of rows and columns in each of memory blocks
5
a
to
5
d
. A word line WL is arranged in correspondence to each of the memory cell rows, whereas a bit line pair BLP constituted by complementary bit lines BL and /BL is arranged in correspondence to each of the memory cell columns.
A global word line GWL is provided common to memory blocks
5
a
to
5
d
along a longitudinal direction (row direction) of a chip. Each word line WL is separately arranged in each of memory blocks
5
a
to
5
d
. Global decoder
10
is arranged at a middle portion of the memory array, i.e., between memory blocks
5
b
and
5
c
, to control activation of global word line GWL. Local decoder zone
20
a
arranged at memory block
5
a
to control activation of word line WL and local decoder zone
20
b
arranged at memory block
5
b
to control activation of word line WL are locally arranged at the border of memory blocks
5
a
and
5
b
. Likewise, local decoder zone
20
c
arranged at memory block
5
c
to control activation of word line WL and local decoder zone
20
d
arranged at memory block
5
d
to control activation of word line WL are locally arranged at the border of memory blocks
5
c
and
5
d.
In a semiconductor memory device shown in
FIG. 6
, global decoder
10
is arranged in correspondence to an end of a memory array constituted by memory blocks
5
a
to
5
d
. The other parts are structured as in the semiconductor memory device shown in FIG.
5
.
In each of the semiconductor memory devices shown in
FIGS. 5 and 6
, memory cell MC is provided with a “SRAM cell” represented by e.g. a high resistance load N-MOS (Metal Oxide Semiconductor) memory cell shown in
FIG. 7
, a TFT (Thin-Film Transistor) load memory cell shown in
FIG. 8
, and a CMOS (Complementary MOS) memory cell shown in FIG.
9
.
Referring to
FIG. 7
, memory cell MC of a high resistance load N-MOS memory cell includes N-channel MOS transistors
31
and
32
each having a gate connected to a corresponding word line WL, a high resistance loads
34
and
35
connected between a power-supply voltage Vcc and respective nodes Ns and /Ns, and N-channel MOS transistors
36
and
37
connected between respective nodes Ns and /Ns and a ground voltage Vss. Nodes Ns and /Ns are electrically coupled to complimentary bit lines BL and /BL, respectively, via transistors
31
and
32
.
Nodes Ns and /Ns are connected to bit lines BL and /BL, respectively, in response to word line WL being activated (to a high level). This allows data on bit lines BL and /BL to be written into respective nodes Ns and /Ns. Once the data is written, it is held by transistors
36
and
37
that are complementarily turned on, and by high resistance loads
34
and
35
, during power input.
It is noted that, in the present description, a high-voltage state (high level) and a low-voltage state (low level) of each signal line, signal, data and the like that are set in binary are also simply referred to as “H” level and “L” level, respectively.
Referring to
FIG. 8
, in a memory cell MC of a TFT load memory cell, TFT loads
41
and
42
formed by P-type thin-film transistors (TFT) are arranged in place of high resistance loads
34
and
35
in the structure of the high resistance load N-MOS memory cell shown in FIG.
7
. This prevents through current from flowing between power-supply voltage Vcc and ground voltage Vss via nodes Ns or /Ns, reducing power consumption at the memory cell.
Referring to
FIG. 9
, in a memory cell MC of a CMOS memory cell, P-channel MOS transistors
45
and
47
are provided in place of high resistance loads
34
and
35
, respectively, in the structure of high resistance load N-MOS memory cell shown in FIG.
7
. The CMOS memory cell is known as having a highly stable structure with a large operation margin.
FIG. 10
is a circuit diagram illustrating a structure of a local decoder zone in the divided word line structure. In
FIG. 10
, local decoder zones
20
a
and
20
b
of local decoder zones
20
a
to
20
d
shown in
FIGS. 5 and 6
are representatively illustrated.
Referring to
FIG. 10
, it is assumed that four word lines WL, associated with one global word line GWL, are arranged in each of memory blocks
5
a
to
5
d.
Local decoder control circuit
15
generates a word line selection signal that is associated with each one of the four word lines associated with one global word line GWL. The word line selection signal is independently generated at each of memory blocks
5
a
to
5
d
, to control selection from each set of four word lines associated with one global word line GWL. Local decoder control circuit
15
generates word line selection signals WSa
0
to WSa
3
to be associated with memory block
5
a
, and word line selection signals WSb
0
to WSb
3
to be associated with memory block
5
b.
Local decoder control circuit
15
selectively activates one of the four word line selection signals associated with a selected memory block, and inactivates the remaining word line selection signals. In addition, word line selection signals associated with a non-selected memory block are inactivated. For instance, when memory block
5
a
is selected, one of word line selection signals WSa
0
to WSa
3
is selectively activated, while the remaining word line selection signals are inactivated.
Though not shown, word line selection signals are generated similarly for each of memory blocks
5
c
and
5
d
. In the description below, word line selection signals WSa
0
to WSa
3
, WSb
0
to WSb
3
, . . . are also simply referred to as, collectively, a word line selection signal WS.
A local decoder
50
is arranged in correspondence to each word line WL. Local decoder
50
activates or inactivates a corresponding word line WL in accordance with the voltage of a corresponding word line selection signal WS and a corresponding global word line GWL. Various structures have conventionally been proposed for such a local decoder which is one kind of row decoder.
Local decoder
50
arranged at local decoder zone
20
a
includes, for example, an NAND gate producing the result of an NAND logical operation of the voltage level of a corresponding one of word line selection signals WSa
0
to WSa
3
and the voltage level of a corresponding global word line GWL, and an inverter driving the voltage of a corresponding word line WL in accordance with an output of the NAND gate.
FIG. 11
is a circuit diagram showing the first configuration example of a local decoder according to the conventional technique.
Referring to
FIG. 11
, local decoder
50
according to the conventional technique includes P-channel MOS transistors
51
and
52
connected in parallel between power-supply voltage Vcc and node N
0
, N-channel MOS transistors
53
and
54
connected in series between node N
0
and ground voltage Vss, and an inverter
55
driving word line WL with one of power

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