Static information storage and retrieval – Interconnection arrangements
Patent
1984-06-28
1987-04-21
Popek, Joseph A.
Static information storage and retrieval
Interconnection arrangements
365 51, G11C 500
Patent
active
046601740
ABSTRACT:
In a semiconductor memory device including word lines (WL) and bit lines (BL), a regular pattern circuit area comprising elements regularly arranged in line with the word lines and/or the bit lines is divided into a plurality of blocks (1-1, 1-2). Provided between the divided blocks are irregular or peripheral circuit areas (2). Provided outside of the divided blocks are pads (P.sub.1 to P.sub.16).
REFERENCES:
patent: 3936812 (1976-02-01), Cox et al.
patent: 4527254 (1985-07-01), Ryan et al.
Nakano Tomio
Sato Kimiaki
Takemae Yoshihiro
Fujitsu Limited
Popek Joseph A.
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