Semiconductor memory device having decreased layout area and...

Details Semiconductor memory device having decreased layout area and... Semiconductor memory device having decreased layout area and...

1999-12-02

2001-02-20

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S231000, C365S189080

Reexamination Certificate

active

06192000

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM), particularly, to a driving circuit of a divisional driving system in which the word lines are divided into a plurality of groups for the driving.
This application is based on Japanese Patent Application No. 10-345624, filed Dec. 4, 1998, the contents of which is incorporated herein by reference.
With increase in the memory capacity of, for example, a DRAM, the memory cell array having a plurality of memory cells arranged therein is enlarged. As a result, the length of the word line for selecting the memory cell also becomes long. The long word line has a large time constant. Therefore, if the word line is driven from one point of the memory cell array, a long time is required for rising the word line to a predetermined potential. A divisional word line driving system in which the word lines are divided into a plurality of groups for the driving has been developed as a system for overcoming the above-noted difficulty.
FIG. 10
shows a general divisional word line driving system applied to, for example, a DRAM of 256 bits. As shown in the drawing, memory cell arrays (MCA)
101
a
to
101
d
comprises a plurality of memory cells (not shown) as well as word lines and bit lines for selecting these memory cells. A plurality of main word lines /MWL (“/MWL” representing a wiring that is rendered active when the signal has a low level) are arranged on the memory cell arrays
101
a
to
101
d
. These main word lines /MWL are selected by main row decoder (MRDC)
102
. Word line driving circuits (WLDRV)
103
a
to
103
e
for driving the word lines within the memory cell arrays are arranged on both sides in the direction of the word lines /MWL of the memory cell arrays
101
a
to
101
d
. Sub-row decoders (SRDC)
104
a
to
104
e
are connected to these word line driving circuits
103
a
to
103
e
, respectively. These sub-row decoders
104
a
to
104
e
selectively output a plurality of word line driving voltages WDRVi and /WDRVi, which are supplied to the word line driving circuits
103
a
to
103
e.
In the divisional word line driving system of the construction described above, the word lines are made hierarchy into a plurality of main word lines /MWL and a plurality of word lines WL, and a single main word line /MWL is selected by the main row decoder
102
. The word line drivers
103
a
to
103
e
serve to supply the word line driving signal WDRV, which is supplied from the sub-row decoders
104
a
to
104
e
, to one of the plural word lines connected to the selected single main word line /MWL.
FIG. 11
exemplifies the word line driving circuit (WLDRV). The circuit shown in the drawing covers the case where, for example, four word line driving voltages WDRV
0
to WDRV
3
supplied from sub-row decoders are selectively outputted. The input terminals of inverter circuits IV
0
to IV
3
are connected to the main word lines/WML, with the output terminals connected to word lines WL
0
to WL
3
. N-channel transistors
105
a
to
105
d
are connected to nodes between these word lines WL
0
to WL
3
and the ground. The word line driving voltages WDRV
0
to WDRV
3
are selectively supplied to the sources of P-channel transistors
106
a
to
106
d
constituting the inverter circuits, with the sources of N-channel transistors
107
a
to
107
d
connected to the ground. Further, inverted word line driving voltage /WDRV
0
to /WDRV
3
are selectively supplied to the gates of the transistors
105
a
to
105
d.
In the circuit of the construction described above, a single main word line /MWL alone selected by the main row decoder among the plural main word lines /MWL is set to a low level, with the non-selected main word lines /MWL being set to a high level. In the inverter circuits of the word line driving circuit (WLDRV) connected to the non-selected main word line /MWL, the N-channel transistors
107
a
to
107
d
are turned on, and the output signal of each inverter circuit goes to a low level. As a result, the word lines connected to the output terminals of these inverter circuits are set to the ground level.
On the other hand, in each of the inverter circuits of the word line driving circuits (WLDRV) connected to the selected main word line /MWL, the P-channel transistors
106
a
to
106
d
are turned on. Since the row decoder causes one of the word line driving voltages WDRVi to be set to a high level, a single word line is driven by the inverter circuit supplied with the word line driving voltage WDRVi of the high level. In this step, since the word line driving voltage /WDRVi has a high level, any of the transistors
105
a
to
105
d
is turned on to cause the other word lines to be set to the ground level. For example, where the word line driving voltage WDRV
0
has a high level, the word line WL
0
is selected. Also, since the word line driving voltages /WDRV
1
to /WDRV
3
have a high level, the transistors
105
b
to
105
d
are turned on to cause the other word lines WL
1
to WL
3
to be set to the ground level.
As described above, the conventional word line driving circuit requires the word line driving voltage WDRV and /WDRV of the complementary level. Therefore, the circuit scale of the sub-row decoder is rendered large and the number of signal lines arranged for the word line driving circuit is increased, leading to the requirement of a large layout area.
The conventional word line driving circuit is also defective in that noise is generated when the word line is driven, as described in the following.
Specifically,
FIG. 12
shows the relationship between the word lines and the bit lines. The reference numerals commonly used in
FIGS. 10 and 12
denote the same members of the circuit. As shown in
FIG. 12
, a plurality of word lines WL arranged in the memory cell arrays
101
a
and
101
b
are alternately connected to the word line driving circuits
103
a
,
103
b
,
103
c
arranged on both sides of the memory cell arrays
101
a
,
101
b
so as to be driven by these word line driving circuits
103
a
,
103
b
,
103
c
. The particular arrangement permits sufficiently the layout pitch of the circuit elements constituting the word line driving circuits. Sense amplifiers (S/A)
120
a
,
120
b
for detecting the potential read on the bit lines are connected to a plurality of bit line pairs BL, /BL arranged to cross the word line WL.
When the signals generated from the memory cells are amplified by the sense amplifiers, the bit line pairs BL, /BL go to a high level or a low level. Thus, a potential difference between the bit line pairs BL and /BL increases. Also, it is unavoidable for a coupling capacitance to be present between the bit line BL and the word line WL. The coupling capacitance between the word line WL and the bit line pairs BL, /BL is larger in the case where the memory cell selected by the word line WL is connected to the bit line than in the case where the memory cell is not connected to the bit line.
A large number of bit line pairs are connected to a single word line. Therefore, where the word line selected by a single word line driving circuit is constructed to be selected in a deviant fashion toward the memory cells connected to one of the bit line, a big noise is generated in the sensing step in the word line driving circuit by the coupling between the bit line and the word line.
FIG. 13
shows the relationship between the memory cell connected to the bit line pair and the selected word line, covering the case where the word line is driven by the word line driving circuits positioned on both sides of the memory cell array. The memory cell is selected at the cross point between the word line marked ◯ and the bit line BL. Also, the coupling capacitance between the word line WL and the bit line BL becomes the greatest at the points marked by the capacitor symbols in FIG.
13
. If the bit line BL has a high level (H) and the bit line /BL has a low level (L) after the sense amplification by the sense amplifier as shown in
FIG.

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