Semiconductor memory device having data protection feature

Static information storage and retrieval – Floating gate – Particular connection

Patent

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Details

365195, 36518504, G11C 1604

Patent

active

059911972

ABSTRACT:
A reset power down mode designating signal and first and second write protect signals are provided to a control circuit. According to the states of these external control signals, the status of unconditional inhibition, unconditional permission, and lock bit (LB) dependency for the protect status of data rewrite is set for each memory block group of a memory array. Therefore, the write protect status can be set in a flexible manner for a nonvolatile semiconductor memory device.

REFERENCES:
patent: 4974208 (1990-11-01), Nakamura et al.
patent: 5592641 (1997-01-01), Fandrich et al.
patent: 5673222 (1997-09-01), Fukumoto et al.

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