Semiconductor memory device having data input/output line...

Details Semiconductor memory device having data input/output line... Semiconductor memory device having data input/output line...

2000-02-25

2001-05-22

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189020

Reexamination Certificate

active

06236616

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory device having a structure in which a data input/output line is shared by a plurality of banks.
2. Description of the Related Art
Generally, in addition to improvement in the operation speed of a central processing unit (CPU), improvement in performance of a memory device for storing data and programs requested by the CPU enhances the performance of a computer system. The amount of input/output data transmitted per unit of time, i.e., bandwidth, must be increased to improve the performance of the memory. The amount of input/output data can be increased by increasing the number of input/output data bits or the access speed.
One representative memory device is a Rambus DRAM (RDRAM). The amount of data read from or written to the RDRAM at one time is directly influenced by the number of input/output lines and defined by a data input/output rule such as ×16 or ×18. When the RDRAM operates at a speed of 400 MHz, data of 2 bytes is transmitted in 1.25 ns (800 MHz) so that a total of 16 bytes of data is transmitted in four cycles externally. Internally, the RDRAM performs an input/output operation of ×128 or ×144 bits at one time at a speed of 100 MHz. Accordingly, data of memory cell bit lines corresponding to the data input/output lines of ×128 or ×144 is selectively transmitted to the data input/output lines via input/output control circuits.
FIG. 1
shows a part of a conventional semiconductor memory device having a bank and an input/output control circuit which controls the bank. Referring to
FIG. 1
, an input/output control circuit
20
selects one bit line among m×n bit line pairs BL in a bank
10
and transmits data of the selected bit line to a data input/output line I/O.
The input/output control circuit
20
includes n m:1 column selectors
30
and a single n:1 column selector
40
. The m:1 column selector
30
selects one bit line among m bit line pairs in response to a first column selection signal CSLFi (i=0−m−1) applied to a first selection gate TFi (i=0−m−1). The selected bit line is connected to the n:1 column selector
40
. The n:1 column selector
40
selects one among the n outputs transmitted from the n m:1 column selectors
30
in response to a second column selection signal CSLSj (j=0−n−1) applied to a second column selection gate TSj (j=0−n−1) and transmits the selected output to the input/output line I/O.
In the input/output control circuit
20
, junction loads on the single input/output line I/O exist in the n second column selection gates TSj (j=0−n−1) and in the m first selection gates TFi (i=0−m−1) connected to a selected second column selection gate TSj (j=0−n−1). The single input/output line I/O is shared by a plurality of banks as shown in FIG.
2
.
Referring to
FIG. 2
, in a memory block DQO, a single input/output line I/O is shared by a plurality of banks
10
through
17
and cell bit lines in the banks
10
through
17
are respectively connected to the input/output line I/O through input/output control circuits
20
through
27
. Accordingly, a load on the single input/output line I/O in the memory block DQO is obtained by multiplying the sum of the junction loads of the n second column selection gates TSj (j=0−n−1) and the junction loads of the m first column selection gates TFi (i=0−m−1) by the number of banks sharing the input/output line I/O, that is, the load on the single input/output line I/O is expressed as a junction load of (m+n)×number of banks. An input/output line I/O having such a large junction load has a problem of slow operation speed and causes power consumption when writing data to memory cells in banks.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device for minimizing power consumption and implementing high speed operation when writing data to memory cells by minimizing a load on an input/output line.
In one embodiment, a semiconductor memory device according to the invention has a memory block including a plurality of banks. In the semiconductor memory device, data of a selected memory cell is input or output via a data input/output line. The memory block is divided into at least two bank groups during a write operation. The data input/output line is divided into at least two local data input/output lines respectively connected to the at least two bank groups, while data is written to the memory cell via a local data input/output line connected to a bank group including the selected memory cell.
In one embodiment, the local data input/output lines are connected to each other while the data is read from the memory cell. Also, the banks of the memory block are grouped by a predetermined memory address.
In another embodiment of the present invention, a semiconductor memory device has at least two memory blocks each comprising a plurality of banks. In the semiconductor memory device, data of a selected memory cell in each memory block is input or output via a data input/output line, and bit lines of at least two banks selected from the plurality of banks in different memory blocks are respectively connected to the data input/output line. The semiconductor memory device includes a switch in each memory block for dividing a memory block into upper and lower bank groups and dividing the data input/output line into upper and lower data input/output lines to separately connect the upper and lower data input/output lines to the respective upper and lower bank groups during write operation, and for connecting the upper and lower data input/output lines to allow the banks in the corresponding memory block to share the data input/output line during read operation. The semiconductor memory device also includes an upper write driver in each memory block for applying write data to a corresponding upper data input/output line connected to a corresponding upper bank group when a memory cell of the upper bank group is selected during the write operation, and a lower write driver for applying the write data to a corresponding lower data input/output line connected to a corresponding lower bank group when a memory cell of the lower bank group is selected during the write operation. In one embodiment, the selected banks belong to different bank groups in different memory blocks.
In one embodiment, the write data is applied to the upper data input/output line via an auxiliary data input/output line by the upper write driver when writing the data in the memory cell in the upper bank group, and write data is applied to the lower data input/output line by the lower write driver when writing data to the memory cell in the lower bank group, whereby the write data is written in the memory cell in the corresponding bank group.
In one embodiment, the switch includes an upper data input/output line selector for applying write data from the upper write driver to the upper data input/output line in response to a write driver enable signal during the write operation. The switch also includes an upper/lower data input/output line connector for disconnecting the lower data input/output line from the upper data input/output line in response to the write driver enable signal during the write operation and connecting the lower data input/output line to the upper data input/output line in response to a write driver enable signal during the read operation.
The upper write driver can apply write data to the upper data input/output line through the switch in response to a write driver enable signal instructing the write operation and a signal for selecting the upper bank group. The lower write driver can apply write data to the lower data input/output line through the switch in response to a write driver enable signal instruc

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