Semiconductor memory device having data erasing mechanism

Details Semiconductor memory device having data erasing mechanism Semiconductor memory device having data erasing mechanism

1995-05-12

1997-04-22

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518524, 36518528, G11C 1140

Patent

active

056234457

ABSTRACT:
In this invention, charges are extracted from the charge storage portion by means of F-N tunnel current, and then avalanche hot carriers are injected into the storage portion.

REFERENCES:
patent: 4173791 (1979-11-01), Bell
patent: 4503519 (1985-03-01), Arakawa
patent: 4742491 (1988-05-01), Liang et al.
patent: 4884239 (1989-11-01), Ono et al.
patent: 5272669 (1993-12-01), Samachisa et al.
patent: 5280446 (1994-01-01), Ma et al.
E. Takeda et al., "Device Performance Degradation Due To Hot-Carrier Injection At Energies Below the Si-SiO.sub.2 Energy Barrier", 1983 International Electron Devices Meeting, Article No. 15.5, pp. 396-399, Dec. 1983.
S. Yamada et al., "A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM", 1991 International Electron Devices Meeting, Article No. 11.4, pp. 307-310, Dec. 1991.
K. Naruke et al., "Restraint of Variation in Threshold Voltage to 1/3, Prevention of Excessive Erasion in Flash Type EEPROM", Nikkei Microdevices, pp. 85-91, Feb. 1992 (English translation attached).

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