Semiconductor memory device having data-compress test mode

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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Details

C365S230030, C365S230050, C365S233100

Reexamination Certificate

active

07573776

ABSTRACT:
A semiconductor memory device includes a plurality of column circuit units selectively operated with a burst length set in a mode register set. A plurality of column control blocks control column access to unit cells, each block activated by each of plural column control signals, and a column control signal generator outputs the plural column control signals to the plural column control blocks in response to a column access command and a burst length.

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Korean Office Action issued in corresponding Korean Patent Application No. KR 10-2006-0040697, issued on Jan. 7, 2008.
Korean Office Action, with English Translation, issued in corresponding Korean Patent Application No. 10-2006-0040697, dated on Jul. 16, 2007.

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