Semiconductor memory device having contact holes of differing st

Details Semiconductor memory device having contact holes of differing st Semiconductor memory device having contact holes of differing st

1998-07-14

2000-02-01

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257296, 257306, 257758, H01L 2348, H01L 27108, H01L 2976, H01L 2352

Patent

active

060206438

ABSTRACT:
A semiconductor memory device comprises a semiconductor substrate, a first conducting layer formed above the main surface of the semiconductor substrate, a second conducting layer formed above the first conducting layer through a first insulating layer and connected to the first conducting layer through a first via-conductor formed in a first contact hole formed in the first insulating layer, and a third conducting layer formed beneath the second conducting layer through a second insulating layer and connected to the second conducting layer through a second via-conductor formed in a second contact hole formed in the second insulating layer, in which an angle formed by a tangent to an inner wall of the first contact hole and a normal to the first conducting layer at a portion of the first conducting layer at which the first contact hole is in contact with the first conducting layer, is larger than an angle formed by a tangent to an inner wall of the second contact hole and a normal to the third conducting layer at a portion of the third conducting layer at which the second contact hole is in contact with the third conducting layer. By virtue of this structure, it is possible to avoid influence of electrical potential variation upon the first conducting layer in the manufacturing process.

REFERENCES:
patent: 5317193 (1994-05-01), Watanabe
Kang, H.K., et al; Highly Manufacturable Process Technology for Reliable 256 Mbit and 1 Gbit DRAMs, 94 IEDM 635-638, 1994.

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