Semiconductor memory device having constant voltage circuit

Details Semiconductor memory device having constant voltage circuit Semiconductor memory device having constant voltage circuit

1998-04-07

2001-03-13

Kim, Jung Ho (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S538000, C327S543000

Reexamination Certificate

active

06201433

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the invention:
The present invention generally relates to a semiconductor memory device having a constant voltage circuit, and more particularly, the present invention relates to an erasable-programmable read-only memory (EPROM) and to a one-time programmable read-only memory (OTPROM).
This application is a counterpart of Japanese application Ser. No. 210720/1997, filed Aug. 5, 1997, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art:
FIG. 2
is a circuit diagram for describing a data reading operation according to a conventional semiconductor memory device.
As shown in
FIG. 2
, the conventional semiconductor memory device, for example an EPROM or an OTPROM, is made up of a memory array
100
having a plurality of memory cells arranged in a matrix of rows the row select signals WL
0
~WL
n
applied thereto and columns having column select signals Y
0
~Y
n
applied thereto. The device also includes a current detecting amplifier
110
electrically connected with the memory array
100
, a constant voltage circuit
120
applying a predetermined potential voltage to drains of the respective memory cells
100
, and a differential amplifier
130
for amplifying outputs from the current detecting amplifier
110
. The conventional semiconductor memory device uses the current detecting amplifier
110
to determine whether or not a storage charge on each of memory cells
100
is present. The conventional semiconductor memory device employs method in which a difference between currents flowing from the selected memory cells
100
to the current detecting amplifier
110
is used to determined whether or not storage charge in present in the memory cells selected by the row select signals WL
0
~WL
n
and column select signals Y
0
~Y
n
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device that can apply a high voltage for the output voltage V
mcd
to drains of each of memory cells even if the power supply voltage V
cc
is a low voltage and further can achieve the improvement of the access velocity for the data reading operation of the semiconductor memory device.
According to one aspect of the present invention, for achieving the above object, there is provided a constant voltage circuit comprising a first transistor of a first conductive type having a drain connected a power supply voltage and a source connected the drain of the respective memory cells, a second transistor of a second conductive type having a source connected the power supply voltage, a gate connected a ground, and a drain connected a gate of the first transistor, and a reference voltage generating circuit turning on and fixing the gate of the first transistor to the predetermined voltage when the power supply voltage is more than a predetermined voltage.
According to another aspect of the present invention, for achieving the above object, there is provided a constant voltage circuit comprising a first constant voltage circuit having a first transistor of a first conductive type, a second transistor of a second conductive type, and a third transistor of a first conductive type, the first transistor having a drain connected to a power supply voltage and a source connected to the drain of the respective memory cells, the second transistor having a source connected to the power supply voltage, a gate connected to a ground, and a drain connected to a gate of the first transistor, the third transistor having a source connected to the ground, a gate connected to the source of the first transistor, and a drain connected to the gate of the first transistor, a second constant voltage circuit having a fourth transistor of a first conductive type and a reference voltage generating circuit, the fourth transistor connecting in parallels with the first transistor, and the reference voltage generating circuit controlling the fourth transistor so as to turn on when a power supply voltage is lower than the predetermined reference voltage, and controlling the fourth transistor so as to turn off when the power supply voltage is higher than the predetermined reference voltage.
Accord in goo another aspect of the present invention, for achieving the above object, there is provided a constant voltage circuit comprising a first transistor of a first conductive type having a drain connected to a power supply voltage and a source connected to the drain of the respective memory cells, a second transistor of a second conductive type having a source connected to the power supply voltage, a gate connected to a ground, and a drain connected to a gate of the first transistor, and a third transistor of a first conductive type having a source connected to the ground, a gate connected to the source of the first transistor, and a drain connected to the gate of the first transistor, a fourth transistor of a first conductive type connecting in parallel with the first transistor, and a potential detecting circuit controlling the fourth transistor so as to turn on when a power supply voltage is lower than the predetermined reference voltage, and controlling the fourth transistor so as to turn off when the power supply voltage is higher than the predetermined reference voltage.
According to another aspect of the present invention, for achieving the above object, there is provided a constant voltage circuit comprising a first transistor of a first conductive type having a drain connected to a power supply voltage and a source connected to the drain of the respective memory cells, a second transistor of a second conductive type having a source connected to the power supply voltage, a gate connected to a ground, and a drain connected to a gate of the first transistor, a third transistor of a first conductive type having a source connected to the ground, a gate connected to the source of the first transistor, and a drain connected to the gate of the first transistor, a fourth transistor of a second conductive type connecting in parallel with the second transistor, and a potential detecting circuit controlling the fourth transistor so as to turn on when a power supply voltage is lower than the predetermined reference voltage, and controlling the fourth transistor so as to turn off when the power supply voltage is higher than the predetermined reference voltage.
According to anther aspect of the present invention, for achieving the above object, there is provided a constant voltage circuit comprising a first transistor of a first conductive type having a drain connected to a power supply voltage and a source connected to the drain of the respective memory cells, a second transistor of a second conductive type having a source connected to the power supply voltage, a gate connected to a ground, and a drain connected to a gate of the first transistor, a third transistor of a first conductive type having a source connected to the ground, a gate connected to the source of the first transistor, and a drain connected to the gate of the first transistor, a fourth transistor of a first conductive type connecting in parallel with the first transistor, and a potential detecting circuit controlling the fourth transistor so as to turn on when an output potential voltage appeared on a common source of the first and second transistors is lower than the predetermined reference voltage, and controlling the fourth transistor so as to turn off when the output potential voltage is higher than the predetermined reference voltage.
According to another aspect of the present invention, for achieving the above object, there is provided a constant voltage circuit comprising a first transistor of a first conductive type having a drain connected to a power supply voltage and a source connected to the drain of the respective memory cells, a second transistor of a second conductive type having a source connected to the power supply voltage, a gate connected to a ground, and a drain connected to a gate of the first transistor, a third transistor of a first condu

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