Semiconductor memory device having configuration suited for...

Details Semiconductor memory device having configuration suited for... Semiconductor memory device having configuration suited for...

2001-04-24

2003-04-08

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060

Reexamination Certificate

active

06545934

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a semiconductor memory device having a configuration suited for high integration.
2. Description of the Background Art
Referring to
FIG. 13
, a prior art semiconductor memory device
700
includes regions
710
,
720
,
721
to
724
,
730
and
740
. The region
710
includes a memory cell array
711
, a column decoder
712
, a row decoder
713
and an input/output circuit zone
714
.
The memory cell array
711
includes a plurality of memory cell blocks
716
and a plurality of sense amplifier groups
717
. The memory cell blocks
716
and the sense amplifier groups
717
are arranged alternately in a column direction
725
. A memory cell block
716
includes a plurality of memory cells arranged in column and row directions
725
and
726
. A sense amplifier group
717
amplifies data outputted from a plurality of memory cells included in the memory cell block
716
.
The column decoder
712
decodes a column address based on an address signal inputted from an address terminal (not shown) to select each of a plurality of bit line pairs (not shown) included in the memory cell array
711
according to the decoded column address. The row decoder
713
decodes a row address based on an address signal inputted from the address terminal to select each of a plurality of word lines (not shown) included in the memory cell array
711
according to the decoded row address.
The input/output circuit zone
714
includes a main amplifier
7141
, a write driver
7142
and an output driver
7143
. The main amplifier
7141
amplifies data outputted from a plurality of memory cells included in the memory cell array
711
to output the amplified data to the output driver
7143
. The write driver
7142
writes data inputted from the input/output terminal (not shown) onto a plurality of memory cells included in the memory cell array
711
. The output driver
7143
outputs data amplified by the main amplifier
7141
to the input/output terminal (not shown).
The regions
720
,
730
and
740
are of the same configuration as the region
710
. The regions
721
to
724
includes respective peripheral circuit groups each constituted of a control circuit, a set-up circuit, a step-down circuit, a redundancy circuit and others.
In the semiconductor memory device
700
, each of the regions
710
,
720
,
730
and
740
includes one input/output circuit zone
714
at one end thereof.
The semiconductor memory device
700
is fabricated, for example, as a semiconductor memory device of a 2 bank configuration. In that case, the memory cell arrays
711
of the respective regions
710
and
720
constitutes a bank A, and the memory cell arrays
711
of the regions
730
and
740
constitute a bank B. Furthermore, the semiconductor memory device
700
is fabricated as a semiconductor memory device of 4 bank configuration. In that case, the memory cell array
711
of the region
710
constitutes a bank A, and the memory cell array
711
of the region
720
a bank B, the memory cell array
711
of the region
730
a bank C and the memory cell array
711
of the region
740
a bank D.
Hence, the prior art semiconductor memory device
700
includes a plurality of banks and is of a configuration including one input/output circuit zone provided in each bank.
FIG. 14
a circuit diagram representing part of the region
710
shown in FIG.
13
. Sense amplifier groups
717
A,
717
B,
717
C,
717
D and
717
E and memory cell blocks
716
A,
716
B,
716
C and
716
D are arranged alternately in the column direction.
Word line drivers
718
A,
718
B,
718
C and
718
D are placed adjacent to the respective memory cell blocks
716
A,
716
B,
716
C and
716
D. Besides, the word line drivers
718
A,
718
B,
718
C and
718
D activate word lines placed in the respective memory cell blocks
716
A,
716
B,
716
C and
716
D according to an row address from the row decoder
713
. When each of the memory cell blocks
716
A,
716
B,
716
C and
716
D includes 8 word lines. The word line drivers
718
A,
718
B,
718
C and
718
D are each inputted with a 4 bit row address from the row decoder
713
. The highest one bit of a 4 bit row address selects each of the memory cell blocks
716
A,
716
B,
716
C and
716
D and the lower three bits further selects 8 word lines in each of the memory cell blocks
716
A,
716
B,
716
C and
716
D which have been selected by the highest one bit.
The memory cell blocks
716
A,
716
B,
716
C and
716
D each include a plurality of memory cells M/C arranged in the row and column directions.
The memory cell blocks
716
A,
716
B,
716
C and
716
D are connected to the input/output circuit zone
714
through global input/output line pairs GIOA, GIOB, GIOC and GIOD.
When a plurality of memory cells M/C, M/C, . . . included in a group
716
A
1
of the memory cell block
716
A are sequentially specified by the column decoder
712
, the row decoder
713
and the word line driver
718
A, a sense amplifier
717
A
1
amplifies data read out from each cell. Furthermore, the sense amplifier
717
A
1
outputs the amplified data to the input/output circuit zone
714
through the global input/output line pair GIOC. Moreover, a plurality of memory cells M/C, M/C, . . . included in a group
716
A
4
of the memory cell block
716
A, likewise, are sequentially specified, a sense amplifier
717
A
2
amplifies data read out from each memory cell. Then, the sense amplifier
717
A
2
outputs the amplified data to the input/output circuit zone
714
through the global input/output line pair GIOD. Furthermore, the sense amplifiers
717
A
1
and
717
A
2
amplify data outputted from not only a plurality of memory cells included in the memory cell block
716
A, but also a plurality of memory cells included in a memory cell block (not shown) residing in the opposed side from the memory cell block
716
A, and output the amplified data to the input/output circuit zone
714
through the global input/output line pairs GIOC and GIOD.
Furthermore, when a plurality of memory cells M/C, M/C, . . . included in a group
716
A
2
of the memory cell block
716
A are sequentially specified, a sense amplifier
717
B
1
amplifies data read out from each memory cell. Then the sense amplifier
717
B
1
outputs the amplified data to the input/output circuit zone
714
through the global input/output line pair GIOB. Besides, the sense amplifier
717
B
1
also amplifies data output from a plurality of memory cells M/C, M/C, . . . included in a group
716
B
2
of the memory cell block
716
B and outputs the amplified data onto the global input/output line pair GIOB.
Furthermore, when a plurality of memory cells M/C, M/C, . . . included in a group
716
A
3
of the memory cell block
716
A are sequentially specified, a sense amplifier
717
B
2
amplifies data read out from each memory cell. Then the sense amplifier
717
B
2
outputs the amplified data to the input/output circuit zone
714
through the global input/output line pair GIOA. Besides, the sense amplifier
717
B
2
also amplifies data output from a plurality of memory cells M/C, M/C, . . . included in a group
716
B
3
of the memory cell block
716
B and outputs the amplified data onto the global input/output line pair GIOA.
Accordingly, data read out from a plurality of memory cells included in the memory cell block
716
A are amplified by the sense amplifier group
717
A or
717
B and the amplified data are outputted to the input/output circuit zone
714
through the global input/output line pairs GIOA, GIOB, GIOC and GIOD.
This applies to a plurality of memory cells included in each of the other memory cell blocks
716
B,
716
C and
717
D in a similar way.
Referring to
FIG. 15
, detailed description will be given of input/output of data to a memory cell.
FIG. 15
shows a case where data is inputted/outputted with 4 bit as a unit. The group
716
A
1
of the memory block
716
A includes a plurality of memory cells. The plurality of memory cells are co

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