Semiconductor memory device having configuration for...

Details Semiconductor memory device having configuration for... Semiconductor memory device having configuration for...

2003-05-16

2004-04-06

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S189011, C365S076000, C327S141000, C327S153000

Reexamination Certificate

active

06717887

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory).
2. Description of the Background Art
Among synchronous dynamic random access memories (SDRAM) operating in synchronization with an externally provided clock signal, the one in which data is input/output in synchronization with a rising edge and a falling edge of an external clock signal is called a double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, hereinafter, referred to as a “DDR SDRAM”).
In the DDR SDRAM, data read from a memory cell array performed in an external clock cycle is based on a prefetch operation in which 2
N
bit data is read to each data output circuit in one read operation.
A DDR SDRAM having N set to 1 is referred to as a DDR-I, while a DDR having N set to 2 is referred to as a DDR-II. The specifications for the DDR-I and the DDR-II are defined by JEDEC (Joint Electron Device Engineering Council).
A clock used in the DDR SDRAM will now be described. The DDR SDRAM has external clocks EXTCLK and EXTZCLK input. Triggered by these external clocks EXTCLK and EXTZCLK, an internal clock CLK as well as delay locked loop (DLL) clocks CLK_P and CLK_N are generated. In reading, in each circuit in the DDR, a clock at an appropriate timing among these clocks is selected, and data in a memory cell is successively pipelined and output to the outside.
The Japanese Patent Laying-Open No. 11-353878 discloses a semiconductor integrated circuit, which, in selecting a clock having a leading phase out of a DLL clock and EXTCLK, selects a DLL clock without comparing phases when a frequency is high. Though the disclosure of the reference is similar to the present invention in selecting the DLL clock, there is a difference in a problem to be solved, a configuration, and an effect thereof.
On the other hand, in order to select DLL clock CLK_P required in a processing at a specific stage in the aforementioned pipeline, a following problem exists.
When it is assumed that a backward amount of DLL clock CLK_P with respect to external clock EXTCLK is represented as Ta, a delay amount of internal clock CLK with respect to EXTCLK is represented as Tb, and a cycle time is represented as Tck, a condition of Ta+Tb<Tck should be satisfied. Therefore, if cycle time Tck is shortened, values for Ta and Tb should also be made smaller.
For example, in the DDR-II, Tck is set to 3 ns (Tck=3 ns). In such an example, a condition of Ta+Tb<3 ns should be satisfied. Under this condition, it is difficult to secure and assure a margin considering process fluctuation, in a variety of operational environments where an operation temperature, an operation voltage, or the like is different.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device accurately selecting a DLL clock corresponding to a desired external clock, even if a cycle time is short.
A semiconductor memory device according to one aspect of the present invention inputs/outputs data in synchronization with a rise and fall of an external clock. The semiconductor memory device includes a first internal clock generation circuit generating a first internal clock having a constant delay amount with respect to the external clock having a cycle T; a second internal clock generation circuit generating a second internal clock having a constant backward amount with respect to the external clock, in order to synchronize a timing for outputting the data to the outside with the external clock; a frequency divider dividing a frequency of the second internal clock into N (≧2) to output cyclically sequenced N frequency division clocks; a first circuit specifying a frequency division clock including a second internal clock pulse having a constant phase difference from a first internal clock pulse corresponding to an external clock pulse indicating a timing for input of a read command, among the N frequency division clocks; and a second circuit selecting the second internal clock pulse corresponding to each external clock pulse after the input of the read command, when the specified frequency division clock is regarded as a starting point.
According to the semiconductor memory device of the present invention, even if cycle T is short, the second internal clock (DLL clock) corresponding to the desired external clock can accurately be selected.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5844859 (1998-12-01), Iwamoto et al.
patent: 5940344 (1999-08-01), Murai et al.
patent: 5963502 (1999-10-01), Watanabe et al.
patent: 11-353878 (1999-12-01), None

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