Semiconductor memory device having column redundancy function

Details Semiconductor memory device having column redundancy function Semiconductor memory device having column redundancy function

2000-01-21

2002-06-11

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030

Reexamination Certificate

active

06404698

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a dynamic semiconductor memory device (DRAM) and particularly, to a semiconductor memory device having a so-called column redundancy function that a defective memory cell is replaced with a spare memory cell on a column by column basis.
A DRAM which is used as a main memory device generally for a personal computer (PC), a work station and the like has experienced capacity increase by quadrupling in each generation. As a result, a DRAM having a capacity of as large as one giga bits has been realized, though in a prototype stage or in a stage of presentation in an institute conference. In such a large capacity DRAM chip, it can be said that there is almost no opportunity that all the memory cells can orderly work. For that reason, there is an unavoidable requirement for a so-called redundancy technique in which a defective memory cell is replaced with a spare memory cell.
Production yield of DRAMs can be improved more as the number of spare memory cells is larger. It is natural, however, that a chip size is increased and cost is also higher. For that reason, there becomes important increase in an efficiency of application of the redundancy technique, that is to realize a highest production yield with use of as small a number of spare memory cells as possible.
The redundancy technique is divided, in a broad sense, into two categories in terms of a method of replacement of a defective memory cell, one of which is a row redundancy technique in which replacement is performed on a word line by word line basis and the other of which is a column redundancy technique in which replacement is performed on a column select line by column select line basis.
At this point, attention will be given to a column redundancy technique. Generally in a column redundancy technique, a defective memory cell is replaced with a spare memory cell with one CSL as a unit.
The number of bit lines selected by one CSL is usually equal to the number of data input/output lines (DQ lines). For this reason, a minimal replacement unit of a column redundancy technique is equal to the number of DQ lines.
Then, consideration will be given to the number of DQ lines. Demands for realization of a DRAM of a higher speed has been present and it is generally said that an access speed of the order of 50 ns to 60 ns is the limit based on the current state of technology. Therefore, there has been used a so-called multiple bit chip provided with many data I/O pins, whereby a band width for data transfer is improved. To increase the number of data I/O pins requires to broaden a bus width inside the DRAM. In addition, to broaden the bus width requires to increase the number of DQ lines.
This has, however, a meaning that a minimal replacement unit of a column redundancy technique is enlarged. As a result, there has remained a problem that a remedy efficiency in a column redundancy technique is decreased.
In such a situation, there has been developed a column redundancy technique whereby a remedy efficiency of a defect product is improved without increase of the number of spare memory cells.
FIGS. 1A and 1B
show examples of the technique. This technique has been disclosed in Jpn. Pat. Appln. Publication No. 5-54691, which will be described below.
FIG. 1A
shows a structure of a main part memory cell array of a DRAM and its peripheral circuits described in the publication. Like this,
FIG. 1B
shows a structure of a spare memory cell array and its peripheral circuits.
In
FIG. 1A
, MC
11
, MC
12
, MC
21
and MC
22
are memory cells respectively; WL
1
and WL
2
are word lines respectively; BL
1
and /BL
1
, BL
2
and /BL
2
are bit line pairs respectively; SA
1
and SA
2
are sense amplifiers respectively connected to the two pairs of bit lines BL
1
and /BL
1
, BL
2
and /BL
2
and sense data read out on the bit lines; DQ
0
and /DQ
0
, DQ
1
and /DQ
1
are DQ line pairs; and Q
11
, Q
12
, Q
21
and Q
22
are transfer gates for effecting controlled connection of the bit line pairs BL
1
and /BL
1
, BL
2
and /BL
2
after data are sensed by the two sense amplifiers SA
1
and SA
2
with the two DQ line pairs DQ
0
and /DQ
0
, DQ
1
and /DQ
1
.
All gates of the four transfer gates Q
11
, Q
12
, Q
21
and Q
22
are commonly connected to one column select line SCL
1
.
In
FIG. 1B
, MCR
11
and MCR
12
are spare memory cells respectively; BLR
1
and /BLR
1
are spare bit line pairs; SAR
1
is a sense amplifier which is connected to the spare bit line pair BLR
1
, /BLR
1
and senses data read out on the spare bit line pairs; QR
11
, QR
12
, QR
21
and QR
22
are transfer gates for effecting controlled connection of the spare bit line pair BLR
1
, /BLR
1
after data is sensed by the sense amplifier SAR
1
with the two DQ line pairs DQ
0
, /DQ
0
, DQ
1
, /DQ
1
.
Gates of two transistor gates QR
11
, QR
12
of the four transfer gates in
FIG. 1B
are commonly connected to a spare column select line CSLR
1
and gates of the residual two transfer gates QR
21
, QR
22
are commonly connected with a spare column select line CSLR
2
.
In such structures, when one of two word lines WL
1
and WL
2
is selected by a row decoder (not shown), data stored in memory cells that are connected to an activated word line are read out to bit lines. For example, when word line WL
1
is selected, data stored in memory cells MC
11
and MC
21
are read out to bit lines BL
1
and BL
2
. Thereafter, the sense amplifiers SA
1
and SA
2
are activated, thereby sensing the data stored in the memory cells.
After the sense amplifiers SA
1
, SA
2
are activated, sensed data on one bit line pair BL
1
, /BL
1
are transferred to the one DQ line pair DQ
0
, /DQ
0
through the transfer gates Q
11
, Q
12
. Sensed data on the other bit line pair BL
2
, /BL
2
are transferred to the other DQ line pair DQ
1
, /DQ
1
through the transfer gates QR
21
, QR
22
.
At this point, when a defective memory cell is present in the memory cell array, the spare memory cells MCR
11
, MCR
12
in the spare memory cell array are used instead of the defective memory cell. In other words, when one or both of the memory cells MC
11
, MC
12
are defective and both memory cells MC
11
, MC
12
are externally tried to be accessed, the spare column select line CSLR
1
is driven by a redundancy control circuit, not shown, and the transfer gates QR
11
, QR
12
are both conductive. Thereby, the spare bit line pair BLR
1
, /BLR
1
are connected with the DQ line pair DQ
0
, /DQ
0
through the two transfer gates QR
11
, QR
12
. As a result, data is read or written on the spare memory cells MCR
11
, MCR
12
instead of the memory cells MC
11
, MC
12
.
On the other hand, when one or both of the memory cells MC
21
, MC
22
are defective, the spare column select line CSLR
2
is driven and the two transfer gates QR
21
, QR
22
are both conductive. The spare bit line pairs BLR
1
, /BLR
1
are connected with the DQ line pair DQ
1
, /DQ
1
through the two transfer gates QR
21
, QR
22
and data are read or written on the spare memory cells MCR
11
, MCR
12
instead of the memory cells MC
21
, MC
22
.
In a conventional DRAM shown in
FIGS. 1A and 1B
, all the four transfer gates Q
11
, Q
12
, Q
21
, Q
22
in the memory cell array are controlled by a signal of one column select line CSL
1
. In general, according to the column redundancy technology, defective columns are replaced in units of the number of columns corresponding to one column select line. If one or more of MC
11
, MC
12
, MC
21
and MC
22
are defective, all bit line pairs that are connected to column select line CSL
1
are replaced with spare columns shown in FIG.
1
B. In this example, two spare columns shown in
FIG. 1B
are needed for the replacement of CSL
1
. In an ordinary replacement method, the first one of the spare columns is connected to a DQ line pair made up of DQ
0
and /DQ
0
, and the second one is connected to a DQ line pair made up of DQ
1
and /DQ
1
.
In the conventional technology, the bit line pairs BLR
1
and /BLR
1
of spare columns are connectable to either one of DQ line pair

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