Semiconductor memory device having circuit for monitoring set va

Details Semiconductor memory device having circuit for monitoring set va Semiconductor memory device having circuit for monitoring set va

1999-01-06

1999-10-26

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518903, 36518905, 36518908, 36518907, 36523006, 365233, G11C 800

Patent

active

059739886

ABSTRACT:
A central control circuit in a semiconductor memory device includes a command decoder and an MRS output circuit. The command decoder decodes an internal control signal. The MRS output circuit generates a control signal for writing a set value of a mode register into a memory cell. According to the control signal, the set value of the mode register is transferred to a data input/output line. A data input/output buffer receives data from the data input/output line, and the data is written into a specific memory cell. The written data is output at a data input/output pin by a normal read operation. A semiconductor memory device allowing externally monitoring a set value of a mode register is thus provided.

REFERENCES:
patent: 5392239 (1995-02-01), Margulis et al.
patent: 5438548 (1995-08-01), Houston
patent: 5625302 (1997-04-01), Covino et al.

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