Semiconductor memory device having bit line pre-charge unit...

Details Semiconductor memory device having bit line pre-charge unit... Semiconductor memory device having bit line pre-charge unit...

2008-01-10

2010-06-29

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185250

Reexamination Certificate

active

07746701

ABSTRACT:
A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more embodiments, a flash memory device that includes a memory cell array, a data register, a state machine, input/output pads, a row decoder, and a column decoder. The memory cell array includes a pre-charge unit that is placed between a plurality of memory cell arrays. The pre-charge unit pre-charges a bit line in a read operation. A data register is separated from the pre-charge unit and is located away from the arrays. Write data are coupled from a data register to the arrays, and read data are coupled from the arrays to the data register.

REFERENCES:
patent: 2006/0077740 (2006-04-01), Lee et al.
patent: 2008/0117686 (2008-05-01), Yamada
patent: 2008/0192550 (2008-08-01), Yamada

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